Methods of Communicating Data Using Inversion and Related Systems

Abstract

A method may be provided to communicate a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus with each group of output data bits and each group of input data bits have an equal data width. Each of the plurality of groups of input data bits at may be received at a data register. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width, the group of input data bits are inverted, the inverted group of input data bits are transmitted as a respective group of output data bits in parallel over the data bus, and an inversion flag associated with the respective group of output data bits is transmitted. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a second logic level different than the first logic level is greater than half of the data width, the group of input data bits is transmitted without inversion as a respective group of output data bits in parallel over the data bus, and a non-inversion flag associated with the respective group of output data bits is transmitted. Related systems are also discussed.

1 . A method of communicating a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus wherein each group of output data bits and each group of input data bits have an equal data width, the method comprising:
 receiving each of the plurality of groups of input data bits at a data register;   for each group of input data bits received at the data register, if a number of data bits of the group of input data bits that changes with respect to respective data bits of a preceding group of output data bits is greater than half of the data width,
 inverting the group of input data bits, 
 transmitting the inverted group of input data bits as a respective group of output data bits in parallel over the data bus, and 
 transmitting an inversion flag associated with the respective group of output data bits; and 
   for each group of input data bits received at the data register, if a number of data bits of the group of input data bits that remains unchanged with respect to respective data bits of a preceding group of output data bits is greater than half of the data width,
 transmitting the group of input data bits without inversion as a respective group of output data bits in parallel over the data bus, and 
 transmitting a non-inversion flag associated with the respective group of output data bits. 
   
     
     
         2 . A method according to  claim 1  wherein the data bus includes a plurality of data transmission lines, wherein transmitting the respective groups of output data bits comprises transmitting data bits of each respective group of output data bits over respective ones of the data transmission lines. 
     
     
         3 . A method according to  claim 1  wherein receiving each of the plurality of groups of input data bits comprises sequentially receiving each of the plurality of groups of input data bits at the data register. 
     
     
         4 . A method according to  claim 1  wherein the inversion and non-inversion flags are transmitted over the data bus in parallel with the associated groups of output data bits. 
     
     
         5 . A method according to  claim 1  wherein receiving each of the plurality of groups of input data bits comprises receiving each of the plurality of groups of input data bits from a memory cell array of an integrated circuit memory device during a read operation, wherein transmitting the respective groups of output data bits comprises transmitting the respective groups of output data bits from the integrated circuit memory device over the data bus to a memory controller. 
     
     
         6 . A method according to  claim 5  further comprising:
 receiving the groups of output data bits and the inversion and non-inversion flags at the memory controller. 
 
     
     
         7 . A method according to  claim 1  wherein the data register comprises a data register of a memory controller, and wherein transmitting the respective groups of output data bits comprises transmitting the respective groups of output data bits from the memory controller over the data bus to an integrated circuit memory device during a write operation to write the respective groups of input data bits to a memory cell array of the integrated circuit memory device. 
     
     
         8 . A method according to  claim 7  further comprising:
 receiving the groups of output data bits and the inversion and non-inversion flags at the integrated circuit memory device. 
 
     
     
         9 . A method according to  claim 1  wherein receiving each of the plurality of groups of input data bits comprises receiving a first plurality of groups of input data bits to be transmitted at a first data rate, and wherein transmitting each group of output data bits corresponding to respective groups of input data bits of the first plurality comprises transmitting each group of output data bits at the first data rate, the method further comprising:
 receiving each of a second plurality of groups of input data bits at the data register to be transmitted at a second data rate different than the first data rate; 
 for each group of input data bits of the second plurality received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width,
 inverting the group of input data bits, 
 transmitting the inverted group of input data bits as a respective group of output data bits in parallel over the data bus at the second data rate, and 
 transmitting an inversion flag associated with the respective group of output data bits; and 
 
 for each group of input data bits of the second plurality received at the data register, if a number of data bits of the group of input data bits having a second logic level different than the first logic level is greater than half of the data width,
 transmitting the group of input data bits without inversion as a respective group of output data bits in parallel over the data bus at the second data rate, and 
 transmitting a non-inversion flag associated with the respective group of output data bits. 
 
 
     
     
         10 . A method according to  claim 9  wherein the first data rate is less than the second data rate. 
     
     
         11 . An electronic data system comprising:
 a data register configured to receive each of a plurality of groups of input data bits;   an inversion controller coupled to the data register, wherein for each group of input data bits received at the data register, if a number of data bits of the group of input data bits that changes with respect to respective data bits of a preceding group of output data bits is greater than half of the data width, the inversion controller is configured to invert the group of input data bits to generate a respective group of output data bits, and wherein for each group of input data bits received at the data register, if a number of data bits of the group of input data bits that remains unchanged with respect to respective data bits of a preceding group of output data bits is greater than half of the data width, the inversion controller is configured to generate a respective group of output data bits without inversion;   an output driver coupled to the inversion controller wherein the output driver is configured to transmit each respective group of output data bits in parallel over a data bus; and   a flag output generator coupled to the inversion controller, wherein the flag output generator is configured to transmit an inversion flag with each group of output data bits generated by inverting the respective group of input data bits, and wherein the flag output generator is configured to transmit a non-inversion flag with each group of output data bits generated without inverting the respective group of input data bits.   
     
     
         12 . An electronic data system according to  claim 11  wherein the data bus includes a plurality of data transmission lines, wherein transmitting the respective groups of output data bits comprises transmitting data bits of each respective group of output data bits over respective ones of the data transmission lines. 
     
     
         13 . An electronic data system according to  claim 11  wherein the data register is configured to sequentially receive each of the plurality of groups of input data bits at the data register. 
     
     
         14 . An electronic data system according to  claim 11  wherein the flag output generator is configured to transmit the inversion and non-inversion flags over the data bus in parallel with the associated groups of output data bits. 
     
     
         15 . An electronic data system according to  claim 11  wherein the data register is further configured to receive each of the plurality of groups of input data bits from a memory cell array of the electronic data system during a read operation, and to transmit the respective groups of output data bits over the data bus to a memory controller. 
     
     
         16 . An electronic data system according to  claim 11  wherein the data register comprises a data register of a memory controller, wherein the data register is further configured to transmit the respective groups of output data bits over the data bus to an integrated circuit memory device during a write operation to write the respective groups of input data bits to a memory cell array of the integrated circuit memory device.