Dual gate finfet

Abstract

A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain. Each gate is formed around approximately three sides of the fin.

1 . A method comprising:
 forming a fin having source and drain regions supported by a substrate;   forming two gates between the source and drain regions, the gates spaced apart surrounding the fin on at least approximately three sides; and   providing independent access to the gates.   
     
     
         2 . The method of  claim 1 , further comprising forming a third independently accessible gate surrounding the fin on at least approximately three sides and laterally spaced with the two gates along the fin between the source and the drain. 
     
     
         3 . The method of  claim 1 , further comprising forming a dielectric spacer between the gates. 
     
     
         4 . The method of  claim 1 , further comprising isolating the fin from the substrate. 
     
     
         5 . The method of  claim 1 , wherein the gates are separated from the fin by a thin gate dielectric layer. 
     
     
         6 . The method of  claim 1 , wherein the gates are formed with different lengths. 
     
     
         7 . The method of  claim 1 , wherein the gates are formed with different work functions. 
     
     
         8 . A method comprising:
 forming a fin over a substrate, the forming of the fin including forming a source region at a first end of the fin and forming a drain region at a second end of the fin;   forming a dielectric layer around approximately three sides of the fin; and   forming a pair of independently accessible gates over the dielectric layer, the independently accessible gates laterally spaced along the fin between the source region and the drain region, each of the independently accessible gates surrounding the fin on at least approximately three sides.   
     
     
         9 . The method of  claim 8 , further comprising connecting each of the pair of independently accessible gates to different circuitry. 
     
     
         10 . The method of  claim 8 , wherein the pair of independently accessible gates includes a first gate and a second gate, further comprising providing the first gate with a first bias and providing the second gate with a second bias. 
     
     
         11 . The method of  claim 10 , wherein the second bias is different from the first bias. 
     
     
         12 . A method comprising:
 forming a fin over a substrate, the forming of the fin including forming a source region at a first end of the fin and forming a drain region at a second end of the fin;   forming a first dielectric layer around approximately three sides of the fin;   forming a second dielectric layer over the top surface of the first dielectric layer; and   forming a pair of gates over the second dielectric layer, the gates laterally spaced along the fin between the source region and the drain region and each of the gates surrounding the fin on at least approximately three sides.   
     
     
         13 . The method of  claim 12 , wherein the first dielectric layer comprises TAO 5  or HFO 2 . 
     
     
         14 . The method of  claim 12 , wherein the second dielectric layer comprises a nitride. 
     
     
         15 . The method of  claim 12 , further comprising forming at least one of a wide source region and a wide drain region, the wide source region and the wide drain region each being wider than the fin and extending beyond the first end and the second end, respectively. 
     
     
         16 . The method of  claim 15 , further comprising disposing a source metal contact layer and a drain metal contact layer over the wide source region and the wide drain region, respectively. 
     
     
         17 . The method of  claim 12 , further comprising providing independent access to the pair of gates.