Semiconductor device

Abstract

The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.

1 - 11 . (canceled) 
     
     
         12 . A semiconductor device comprising a semiconductor memory section that has a write mode, a read mode and a bypass mode, wherein
 said semiconductor memory section includes:   a memory cell array having a plurality of memory cells arranged in a predetermined direction;   an input port into which data is inputted;   an output port from which data is outputted;   a plurality of read word lines respectively connected to said plurality of memory cells in the memory cell array;   a plurality of write word lines respectively connected to said plurality of memory cells in said memory cell array;   a decoder circuit which activates any one of said plurality of write word lines in said write mode, and activates any one of said plurality of read word lines in said read mode;   an input buffer circuit which receives data having been inputted into said input port, and outputs the received data;   a write bit line which extends from said input buffer circuit to said memory cell array, and transmits data outputted from said input buffer circuit to said memory cell array;   an output buffer circuit which outputs received data to said output port; and   a read bit line which extends from said memory cell array to said output buffer circuit, and transmits data from said memory cell array to said output buffer circuit,   said read bit line is extended from said memory cell array to said input buffer circuit, and   said input buffer circuit outputs data, having been inputted into said input port, not to said read bit line but to said write bit line in said write mode, and outputs data, having been inputted into said input port, to said read bit line in said bypass mode.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein
 said input buffer circuit has:   a bit line switch circuit which does not output data, having been inputted into said input port, to said read bit line in said read mode and said write mode, and outputs the data to said read bit line in said bypass mode; and   a bit line driver circuit which outputs data, having been inputted into said input port, to said write bit line based upon a control signal in said write mode.