Automatic control of clock duty cycle

Abstract

In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

1 . A clock synthesizer comprising:
 a phase-locked loop forward circuit path configured to generate an intermediate clock signal based on a reference clock signal and a feedback clock signal;   a duty cycle correction circuit configured to adjust the falling edge of the intermediate clock signal to produce an output clock signal; and   a feedback circuit path configured to apply the output clock signal to the phase-locked loop forward circuit path as the feedback clock signal.   
     
     
         2 . The clock synthesizer or  claim 1 , wherein the feedback circuit path comprises a frequency divider configured to generate a frequency-divided output clock signal based on the output clock signal, and wherein the feedback circuit path is further configured to apply the frequency-divided output clock signal to the phase-locked loop forward circuit path as the feedback clock signal.