Method of fabricating a precision buried resistor

Abstract

The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

1 . A semiconductor structure comprising:
 a semiconductor substrate including at least a well region; and   a buried resistor located in a region of said semiconductor substrate that is beneath said well region, wherein buried resistor has a sheet resistance tolerance of less than 10%.   
     
     
         2 . The semiconductor substrate of  claim 1  wherein said substrate comprises a bulk semiconductor material. 
     
     
         3 . The semiconductor substrate of  claim 2  wherein said bulk semiconductor material comprises a Si-containing semiconductor material. 
     
     
         4 . The semiconductor structure of  claim 2  wherein said semiconductor substrate and said buried resistor have the same polarity. 
     
     
         5 . The semiconductor structure of  claim 2  wherein said semiconductor substrate and said buried resistor have different polarities. 
     
     
         6 . The semiconductor structure of  claim 1  wherein said semiconductor substrate comprises a semiconductor-on-insulator (SOI) substrate that includes a buried insulating layer separating a top semiconductor layer from a bottom semiconductor layer. 
     
     
         7 . The semiconductor structure of  claim 6  wherein said top semiconductor layer of said SOI substrate comprises a Si-containing semiconductor material. 
     
     
         8 . The semiconductor structure of  claim 6  wherein said semiconductor substrate and said buried resistor have the same polarity. 
     
     
         9 . The semiconductor structure of  claim 6  wherein said semiconductor substrate and said buried resistor have different polarities. 
     
     
         10 . The semiconductor structure of  claim 1  wherein said well region has end portions that are in contact with end portions of the buried resistor. 
     
     
         11 . The semiconductor structure of  claim 10  wherein said end portions of the well region have the same polarity as that of the buried resistor. 
     
     
         12 . The semiconductor structure of  claim 1  wherein said well region is contact along an entire length of said buried resistor. 
     
     
         13 . The semiconductor structure of  claim 1  wherein said semiconductor substrate includes an epitaxial semiconductor layer in which a part of said well region is located. 
     
     
         14 . The semiconductor structure of  claim 1  wherein well region is located with a top semiconductor layer of an SOI substrate and said buried resistor is located in a bottom semiconductor layer of said SOI substrate. 
     
     
         15 . The semiconductor structure of  claim 1  wherein said buried resistor is electrically isolated from said substrate by a tub region. 
     
     
         16 . The semiconductor structure of  claim 1  wherein said buried resistor is a bottom electrode plate of a metal-insulator-metal capacitor. 
     
     
         17 . The semiconductor structure of  claim 1  further comprising a field effect transistor located on an upper surface of said substrate.