US2011108794A1PendingUtilityA1

Phase Changeable Memory Devices

Assignee: HA YONGHOPriority: Feb 25, 2003Filed: Jan 20, 2011Published: May 12, 2011
Est. expiryFeb 25, 2023(expired)· nominal 20-yr term from priority
H10N 70/8828H10N 70/8418H10N 70/821H10N 70/231H10N 70/061H10B 63/30H10D 84/00
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Claims

Abstract

Phase changeable memory devices are provided. A phase changeable memory device may include two first electrodes spaced apart from each other. The phase changeable memory device may also include a common phase changeable material contacting a sidewall of each of the two first electrodes. The phase changeable memory device may further include a second electrode overlying the common phase changeable material. A top surface of each of the two first electrodes may not physically contact the phase changeable material.

Claims

exact text as granted — not AI-modified
1 . A phase changeable memory device, comprising:
 two first electrodes spaced apart from each other;   a common phase changeable material contacting a sidewall of each of the two first electrodes; and   a second electrode overlying the common phase changeable material,   wherein a top surface of each of the two first electrodes does not physically contact the phase changeable material.   
     
     
         2 . The phase changeable memory device of  claim 1 , wherein a bottom surface of the common phase changeable material is lower than a bottom surface of each of the two first electrodes. 
     
     
         3 . The phase changeable memory device of  claim 1 , wherein the common phase changeable material comprises chalcogenide material. 
     
     
         4 . The phase changeable memory device of  claim 1 , further comprising a silicon nitride material contacting a bottom surface of the common phase changeable material. 
     
     
         5 . The phase changeable memory device of  claim 1 , further comprising a bit line electrically connected to the second electrode. 
     
     
         6 . The phase changeable memory device of  claim 1 , further comprising:
 a first impurity diffusion region in a semiconductor substrate electrically connected to one of the two first electrodes; and   a second impurity diffusion region in the semiconductor substrate electrically connected to another one of the two first electrodes,   wherein the first and the second impurity diffusion regions are spaced apart from each other.   
     
     
         7 . The phase changeable memory device of clam  1 , further comprising:
 a first access device operationally coupled to one of the two first electrodes; and   a second access device operationally coupled to another of the two first electrodes.   
     
     
         8 . The phase changeable memory device of  claim 1 , wherein a contact area between the common phase changeable material and one of the two first electrodes is smaller than a top surface area of one of the two first electrodes.

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