Processor Architecture for Executing Wide Transform Slice Instructions

Abstract

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

1 . A processor comprising:
 a data path having a first bit width;   a wide operand storage coupled to the data path for storing a wide operand, the wide operand storage having a capability of storing a wide operand having a size with a number of bits greater than the first bit width;   a register file having the first bit width, the register file being connected to the data path and including storage for a wide operand specifier for specifying an address of the wide operand in a memory; and   an execution unit coupled through the data path to the register file, when executing an instruction the execution unit referencing the register file to obtain information to allow retrieval of the wide operand from the memory and storage of the wide operand in the wide operand storage.   
     
     
         2 . A processor as in  claim 1  wherein the wide operand specifier includes both an address for the wide operand and an indicia of the size of the wide operand. 
     
     
         3 . A processor as in  claim 2  wherein the wide operand specifier comprises the address of the wide operand catenated to the indicia of the size of the wide operand. 
     
     
         4 . A processor as in  claim 3  wherein the indicia of the size of the wide operand includes a number indicative of one half a total number of bytes in the wide operand catenated to a number indicative of a shape of the wide operand. 
     
     
         5 . A processor as in  claim 1  further comprising a results register coupled to the execution unit, the results register having a capability of storing results having a size greater than the width greater than the first bit width. 
     
     
         6 . A processor as in  claim 1  further comprising a second wide operand storage coupled to the data path for storing second wide operands that have a size with a number of bits greater than the first width; wherein the second wide operands are specified by a second wide operand specifier. 
     
     
         7 . A processor as in  claim 1  wherein intermediate results of execution operations by the processor may have bit widths greater than the first bit width. 
     
     
         8 . A processor as in  claim 1  wherein after first being used the wide operand is at least temporarily retained in the wide operand storage to enable subsequent execution operations to access the wide operand by reading from the wide operand storage. 
     
     
         9 . A processor as in  claim 1  wherein a processor instruction set and algorithms it implements are not constrained by the size of the register file. 
     
     
         10 . A processor as in  claim 9  wherein the wide operand has a greater size in bits than any register in the register file. 
     
     
         11 . A processor as in  claim 1  further including a multiplier array for high precision arithmetic of which only portions are used for low precision arithmetic 
     
     
         12 . A processor as in  claim 1  wherein when the processor references the register file an indication is provided as to whether the wide operand stored in the wide operand storage may be reused. 
     
     
         13 . A processor comprising:
 a data path having a first width;   a first wide operand storage and a second wide operand storage, each coupled to the data path and each capable of storing a wide operand having a width greater than the first width;   a register file having the first width, the register file being connected to the data path and including storage for at least two wide operand specifiers for specifying respective addresses for two wide operands and including indicia of the sizes of the respective two wide operands; and   an execution unit coupled through the data path to the register file, when executing an instruction the execution unit referencing the register file to obtain information to allow retrieval of the wide operands from the memory and storage of them in the first wide operand storage and the second wide operand storage.   
     
     
         14 . A processor comprising:
 an execution unit for executing instructions;
 a data path having a first bit width coupled to the execution unit; 
 a wide operand storage coupled to the data path for, in response to execution of an instruction storing a wide operand, the wide operand storage having a capability of storing an wide operand having a size having a larger number of bits than the first bit width; 
 a register file connected to the data path and also having the first bit width, the register file including storage at an addressable location for a wide operand specifier, the wide operand specifying an address of a wide operand in a memory and an indicia of its size; 
 and wherein when executing a first instruction requiring the wide operand, the register provides the address of the wide operand in the memory; and when a subsequent instruction references the wide operand, the execution unit checks the register file to determine if the wide operand already stored in the wide operand storage may be reused. 
   
     
     
         15 . A processor as in  claim 14  wherein the execution unit performs an operation which combines the wide operand with another operand, constrains the result to the first width, and stores the result in a results register. 
     
     
         16 . A processor as in  claim 14  wherein the execution unit performs an operation which combines the wide operand with another wide operand to produce a result having a width greater than the first bit width and stores the result in the wide operand storage. 
     
     
         17 . A processor as in  claim 15  wherein the execution unit reads the memory in multiple cycles to retrieve wide operands stored therein over the data path. 
     
     
         18 . A processor as in  claim 17  wherein the execution unit writes the result into the register file in multiple cycles. 
     
     
         19 . A processor as in  claim 15  wherein the execution unit writes the result into the wide operand storage in multiple cycles. 
     
     
         20 . A processor as in  claim 15  wherein the processor addresses the wide operand storage and the second wide operand storage at the same time to retrieve wide operands from each. 
     
     
         21 - 23 . (canceled)