Wiring forming system and wiring forming method for forming wiring on wiring board
Abstract
A wiring forming system comprises: maskless exposure unit which directly exposes an unexposed board by using exposure data generated based on design data relating to an wiring board; post-development inspect unit which tests the board after development, by using the exposure data and the image data of the board exposed and developed by the maskless exposure unit; etching unit which etches the developed board; and post-etching inspect unit which tests an etching pattern formed on the etched board, by using etching inspect data generated based on the design data and the image data of the board etched by the etching unit.
Claims
exact text as granted — not AI-modified1 . A wiring forming system for forming wiring on a wiring board, comprising:
maskless exposure unit which directly exposes an unexposed board by using exposure data generated based on design data relating to said wiring board; and post-development inspect unit which tests said board after development, by using said exposure data and image data of said board exposed and developed by said maskless exposure unit.
2 . A wiring forming system as claimed in claim 1 , further comprising:
etching unit which etches said developed board; and post-etching inspect unit which tests an etching pattern formed on said etched board, by using etching inspect data generated based on said design data and image data of said board etched by said etching unit.
3 . A wiring forming method for forming wiring on a wiring board, comprising:
a post-development inspect step for testing a board exposed and developed, by using design data that is used for maskless exposure of an unexposed board; and a post-etching inspect step for testing an etched board produced by etching said developed board, by using said design data.
4 . A wiring forming method as claimed in claim 3 , further comprising an exposure data verification step for verifying the accuracy of said exposure data generated based on said design data.
5 . A wiring forming method as claimed in claim 3 , further comprising an etching inspect data verification step for verifying the accuracy of said etching inspect data generated based on said design data.
6 . A wiring forming method as claimed in claim 3 , further comprising a resizing rule generating step for, based on said design data and image data of said etched board, estimating optimum design data for obtaining said etched board with a desired result, and generating a resizing rule that indicates how said design data currently used should be corrected to obtain said optimum design data.
7 . A wiring forming method for forming wiring on a wiring board, comprising:
a maskless exposure step for directly exposing an unexposed board by using exposure data generated based on design data relating to said wiring board; a post-development inspect step for testing said board after development, by using said exposure data and image data of said board exposed and developed in said maskless exposure step; an etching step for etching said developed board; and a post-etching inspect step for testing an etching pattern formed on said etched board, by using etching inspect data generated based on said design data and image data of said board etched in said etching step.
8 . A wiring forming method as claimed in claim 7 , further comprising an exposure data verification step for verifying the accuracy of said exposure data generated based on said design data.
9 . A wiring forming method as claimed in claim 7 , further comprising an etching inspect data verification step for verifying the accuracy of said etching inspect data generated based on said design data.
10 . A wiring forming system as claimed in claim 7 , further comprising a resizing rule generating step for, based on said design data and image data of said etched board, estimating optimum design data for obtaining said etched board with a desired result, and generating a resizing rule that indicates how said design data currently used should be corrected to obtain said optimum design data.
11 . A wiring forming system for forming wiring on a wiring board, comprising:
inkjet patterning unit which forms a wiring pattern by inkjetting on a pre-drawing board by using drawing data generated based on design data relating to said wiring board; and post-patterning inspect unit which tests said wiring pattern formed by inkjetting on said board, by using said design data and image data of said post-patterning board on which said wiring pattern has been formed by said inkjet patterning unit.
12 . A wiring forming system as claimed in claim 11 , wherein said design data comprises predetermined wiring information for at least one unit wiring board to be formed in said wiring board and predetermined pad layout information for an electronic component to be mounted or formed on said unit wiring board.
13 . A wiring forming system as claimed in claim 11 , further comprising dynamic routing rules data generating unit which, based on said design data and a position on said post-patterning board at which said electronic component is to be mounted or formed on said unit wiring board, generates dynamic routing rules data that indicates how said wiring should be changed to achieve a desired interconnection pattern.
14 . A wiring forming system as claimed in claim 11 , further comprising resizing rule generating unit which, based on said design data and the image data of said post-patterning board, estimates optimum design data for obtaining said post-patterning board with a desired result, and generates a resizing rule that indicates how said design data currently used should be corrected to obtain said optimum design data.
15 . A wiring forming system as claimed in claim 11 , wherein said inkjet patterning unit includes scaling correction value generating unit which measures shrinkage/expansion of said post-patterning board relative to said pre-patterning board and generates a scaling correction value for correcting the position and shape of said drawing data based on said measured shrinkage/expansion.
16 . A wiring forming system as claimed in claim 11 , wherein said inkjet patterning unit includes misalignment data generating means which, prior to inkjet patterning, measures a displacement between a reference position on a drawing stage at which said pre-drawing board should normally be placed and a position on said drawing board at which said pre-drawing board is actually placed, and which generates misalignment data based on said measured displacement.
17 . A wiring forming system as claimed in claim 16 , wherein said inkjet patterning unit includes mechanical correcting unit which, prior to inkjet patterning, performs correction so as to bring the position of said pre-drawing board as close as possible to said reference position, by mechanically displacing, based on said misalignment data, said drawing stage on which said pre-drawing board is actually placed.
18 . A wiring forming system as claimed in claim 11 , wherein said inkjet patterning unit comprises a plurality of inkjet heads which are arranged so as to form patterns in respectively designated areas on a surface of said pre-drawing board, and which perform inkjet patterning in parallel fashion.
19 . A wiring forming system as claimed in claim 18 , further comprising an input database which stores resized design data generated by correcting said design data in accordance with said resizing rule.
20 . A wiring forming system as claimed in claim 19 , wherein said input data base further stores at least one kind of data selected from the group consisting of: job deck information data indicating how data relating to each unit wiring board should be arranged on said wiring board; position alignment information data; and wiring and placement information data for a passive device to be mounted or formed on said unit wiring board.
21 . A wiring forming system as claimed in claim 20 , wherein said input data base stores said data by dividing each kind of data so as to allocate the same among said respective inkjet heads.
22 . A wiring forming system as claimed in claim 21 , further comprising a raster image processor which is provided for each of said inkjet heads, and which drives said inkjet head by taking as an input said each kind of data allocated to said inkjet head.
23 . A wiring forming system as claimed in claim 22 , wherein said raster image processor includes reading unit which, in synchronism with operation of said inkjet patterning unit, reads out said design data, said resized design data, said scaling correction value, and said dynamic routing data, allocated to said inkjet head.
24 . A wiring forming system as claimed in claim 23 , wherein said reading unit further reads out said misalignment data in synchronism with operation of said inkjet patterning unit.
25 . A wiring forming system as claimed in claim 24 , wherein, using at least one of said scaling correction value, said dynamic routing rules data, and said misalignment data, said raster image processor distorts graphic data of said resized design data, dislocates the position of said graphic data, and thereby generates said drawing data allocated to said designated patterning area on the surface of said pre-drawn board.
26 . A wiring forming system as claimed in claim 24 , wherein, using at least one of said scaling correction value, said dynamic routing rules data, and said misalignment data, said raster image processor distorts graphic data of said design data, dislocates the position of said graphic data, and thereby generates said post-patterning inspect data.
27 . A wiring forming system as claimed in claim 25 , wherein said drawing data has a vector data format extracting a contour of said graphic data.
28 . A wiring forming system as claimed in claim 27 , further comprising a vectorizer which extracts the contour of said image data of said post-patterning board, and generates image data having a vector data format.
29 . A wiring forming system as claimed in claim 11 , wherein said post-patterning inspect unit includes inspect result outputting means which outputs a inspect result for said post-patterning board.
30 . A wiring forming system as claimed in claim 11 , wherein said post-patterning inspect unit includes result storing unit which stores information relating to said post-patterning board if said post-patterning board is tested defective.
31 . A wiring forming system as claimed in claim 11 , further comprising drawing data verification unit which verifies the accuracy of said drawing data generated based on said design data.
32 . A wiring forming system as claimed in claim 31 , wherein said drawing data verification unit includes first verification result outputting means which outputs a verification result for the accuracy of said drawing data.
33 . A wiring forming system as claimed in claim 11 , further comprising post-patterning inspect data verification unit which verifies the accuracy of said post-patterning inspect data generated based on said design data.
34 . A wiring forming system as claimed in claim 25 , further comprising a verification raster image processor which, based on an algorithm different from the algorithm of said raster image processor for generating said drawing data, generates drawing data and outputs the same as verification drawing data, and wherein said post-patterning inspect unit includes switching unit which switches data to be input together with said drawing data between the image data of said post-patterning board and said verification drawing data, and drawing data verification unit which verifies the accuracy of said drawing data by using said drawing data and said verification drawing data when an input to said post-patterning inspect unit is switched to said verification drawing data by said switching unit.
35 . A wiring forming system as claimed in claim 34 , wherein said drawing data verification unit includes first verification result outputting means which outputs a verification result for the accuracy of said drawing data.
36 . A wiring forming system as claimed in claim 25 , further comprising:
a verification raster image processor which, based on an algorithm different from the algorithm of said raster image processor for generating said drawing data, generates drawing data and outputs the same as verification drawing data; and drawing data verification unit which verifies the accuracy of said drawing data by using said drawing data and said verification drawing data.
37 . A wiring forming system as claimed in claim 36 , wherein said drawing data verification unit includes first verification result outputting means which outputs a verification result for the accuracy of said drawing data.
38 . A wiring forming system as claimed in claim 34 , further comprising:
first bitmap data generating means which generates bitmap data for said drawing data; second bitmap data generating means which generates bitmap data for said verification drawing data generated by said verification raster image processor; and bit-level drawing data verification unit which verifies the accuracy of said drawing data at bit level by using the bitmap data of said drawing data generated by said first bitmap data generating means and the bitmap data of said verification drawing data generated by said second bitmap data generating means.
39 . A wiring forming system as claimed in claim 38 , wherein said bit-level drawing data verification unit includes second verification result outputting means which outputs a verification result for the accuracy of said drawing data at the bit level.
40 . A wiring forming system as claimed in claim 38 , wherein said bit-level drawing data verification unit further includes a inspect rule data base which stores a inspect rule that defines an allowable level of difference between the bitmap data of said drawing data generated by said first bitmap data generating means and the bitmap data of said verification drawing data generated by said second bitmap data generating means, and wherein said bit-level drawing data verification unit verifies the accuracy of said drawing data at the bit level in accordance with said inspect rule.
41 . A wiring forming system as claimed in claim 36 , further comprising:
first bitmap data generating means which generates bitmap data for said drawing data; second bitmap data generating means which generates bitmap data for said verification drawing data generated by said verification raster image processor; and bit-level drawing data verification unit which verifies the accuracy of said drawing data at the bit level by using the bitmap data of said drawing data generated by said first bitmap data generating means and the bitmap data of said verification drawing data generated by said second bitmap data generating means.
42 . A wiring forming system as claimed in claim 41 , wherein said bit-level drawing data verification unit includes second verification result outputting means which outputs a verification result for the accuracy of said drawing data at the bit level.
43 . A wiring forming system as claimed in claim 41 , wherein said bit-level drawing data verification unit further includes a inspect rule data base which stores a inspect rule that defines an allowable level of difference between the bitmap data of said drawing data generated by said first bitmap data generating means and the bitmap data of said verification drawing data generated by said second bitmap data generating means, and wherein said bit-level drawing data verification unit verifies the accuracy of said drawing data at the bit level in accordance with said inspect rule.
44 . A wiring forming system for forming wiring on a wiring board, comprising:
inkjet patterning unit which forms a wiring pattern by inkjetting on a pre-drawn board by using drawing data generated based on design data relating to said wiring board; and post-patterning inspect unit which tests said wiring pattern formed by inkjetting on said board, by using said design data and image data of said post-patterning board on which said wiring pattern has been formed by said inkjet patterning unit.
45 . A wiring forming method for forming wiring on a wiring board, comprising:
a post-patterning inspect step for testing a wiring pattern formed by inkjetting on said board, by using design data that is used to form said wiring pattern by inkjetting on a pre-drawn board.
46 . A wiring forming method as claimed in claim 45 , further comprising a drawing data verification step for verifying the accuracy of said drawing data generated based on said design data.
47 . A wiring forming method as claimed in claim 45 , further comprising a design data generating step for generating said design data.
48 . A wiring forming method as claimed in claim 45 , further comprising a resizing rule generating step for, based on said design data and image data of said post-patterning board, estimating optimum design data for obtaining said post-patterning board with a desired result, and generating a resizing rule that indicates how said design data currently used should be corrected to obtain said optimum design data.
49 . A wiring forming method for forming wiring on a wiring board, comprising:
an inkjet patterning step for forming a wiring pattern by inkjetting on a pre-drawing board by using drawing data generated based on design data relating to said wiring board; and a post-patterning inspect step for testing said wiring pattern formed by inkjetting on said board, by using said drawing data and image data of said post-patterning board on which said wiring pattern has been formed in said inkjet patterning step.
50 . A wiring forming method as claimed in claim 49 , further comprising a drawing data verification step for verifying the accuracy of said drawing data generated based on said design data.
51 . A wiring forming method as claimed in claim 49 , further comprising a resizing rule generating step for, based on said design data and the image data of said post-patterning board, estimating optimum design data for obtaining said post-patterning board with a desired result, and generating a resizing rule that indicates how said design data currently used should be corrected to obtain said optimum design data.Join the waitlist — get patent alerts
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