Method of fabricating semiconductor device

Abstract

A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

1 . A method of fabricating a semiconductor device, comprising:
 providing a substrate;   forming a MOSFET in the substrate, wherein the MOSFET comprises a gate structure and a source/drain region;   after the MOSFET is formed, performing a PAI process to amorphize a gate conductive layer of the gate structure;   after the PAI process is performed, forming an STS on the substrate; and   performing an RTA process.   
     
     
         2 . The method of fabricating a semiconductor device as claimed in  claim 1 , wherein the atom used in the PAI process is selected from a group consisting of Ge, As, C, Sb, and a combination thereof. 
     
     
         3 . The method of fabricating a semiconductor device as claimed in  claim 1 , wherein the source/drain region comprises a source/drain extension region and a source/drain contact region, and the energy for performing the PAI process is less than the energy for performing an ion implantation process for forming the source/drain contact region. 
     
     
         4 . The method of fabricating a semiconductor device as claimed in  claim 1 , wherein the source/drain region comprises a source/drain extension region and a source/drain contact region, and the energy for performing the PAI process is greater than the energy for performing an ion implantation process for forming the source/drain extension region. 
     
     
         5 . The method of fabricating a semiconductor device as claimed in  claim 4 , wherein the energy for performing the PAI process is between the energy for performing an ion implantation process for forming the source/drain extension region and the energy for performing an ion implantation process for forming the source/drain contact region. 
     
     
         6 . The method of fabricating a semiconductor device as claimed in  claim 5 , wherein the atom used in the PAI process is Ge, and the energy for the PAI process is about 5-20 KeV. 
     
     
         7 . The method of fabricating a semiconductor device as claimed in  claim 1 , wherein the material of the STS comprises Si x O y  or Si x N y . 
     
     
         8 . The method of fabricating a semiconductor device as claimed in  claim 1 , wherein the method of forming the MOSFET comprises:
 forming the gate structure on the substrate, wherein the gate structure comprises a gate dielectric layer, a gate conductive layer, and a first spacer;   forming a source/drain contact region in the substrate;   removing the first spacer;   forming a source/drain extension region in the substrate around the gate conductive layer; and   forming a second spacer at the sidewalls of the gate conductive layer.