Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control

Abstract

A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.

1 . A non-volatile memory semiconductor device comprising:
 a semiconductor substrate having a channel; and   a gate stack above the channel, the gate stack comprising a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer comprising a compound including silicon and nitrogen, a charge blocking layer above the charge trapping layer containing an oxide of a charge blocking component, a control gate above the charge blocking layer, and an interface region between the charge trapping layer and the charge blocking layer, wherein the interface region is intentionally incorporated into the gate stack and comprises a compound including silicon, nitrogen and the charge blocking component.   
     
     
         2 . The non-volatile memory semiconductor device of  claim 1 , wherein the semiconductor substrate comprises silicon. 
     
     
         3 . The non-volatile memory semiconductor device of  claim 1 , wherein the tunnel layer comprises at least one compound selected from SiO 2 , Al 2 O 3 , MgO, SrO, BaO, TiO, Ta 2 O 5 , BaTiO 3 , BaZrO 3 , ZrO 2 , HfO 2 , Y 2 O 3 , ZrSiO 4 , HfSiO 4  and LaAlO 3 . 
     
     
         4 . The non-volatile memory semiconductor device of  claim 1 , wherein the tunnel layer comprises at least one silicon nitride compound having a chemical formula of Si x N y  or Si x N y H z . 
     
     
         5 . The non-volatile memory semiconductor device of  claim 1 , wherein the tunnel layer comprises SiON. 
     
     
         6 . The non-volatile memory semiconductor device of  claim 1 , wherein the tunnel layer comprises:
 a first tunnel sub-layer comprising at least one compound selected from the group consisting of SiO 2  and SiON;   a second tunnel sub-layer comprising at least one compound selected from the group consisting of Al 2 O 3 , MgO, SrO, BaO, TiO, Ta 2 O 5 , BaTiO 3 , BaZrO 3 , ZrO 2 , HfO 2 , Y 2 O 3 , ZrSiO 4 , HfSiO 4 , LaAlO 3  and Si x N y ; and   a third tunnel sub-layer comprising at least one compound selected from the group consisting of SiO 2  and SiON.   
     
     
         7 . The non-volatile memory semiconductor device of  claim 1 , wherein the tunnel layer has a thickness in the range of about 5 nm to 12 nm. 
     
     
         8 . The non-volatile memory semiconductor device of  claim 1 , wherein the charge trapping layer comprises:
 a first trapping sub-layer adjacent to the tunnel layer, the first trapping sub-layer having a first composition engineered to provide a low charge trap density to increase retention of information; and   a second trapping sub-layer having a second composition adjacent to the interface region.   
     
     
         9 . The non-volatile memory semiconductor device of  claim 8 , wherein the second trapping sub-layer is engineered to provide a low charge trap generation and minimize endurance degradation of the device. 
     
     
         10 . The non-volatile memory semiconductor device of  claim 8 , wherein the second trapping sub-layer has a high charge trap density for improved memory window. 
     
     
         11 . The non-volatile memory semiconductor device of  claim 8 , wherein the first trapping sub-layer comprises stoichiometric silicon nitride. 
     
     
         12 . The non-volatile memory semiconductor device of  claim 8 , wherein the first trapping sub-layer comprises a nitrogen-rich silicon nitride compound containing about the same as or more nitrogen on an atomic percentage basis than is present in stoichiometric silicon nitride. 
     
     
         13 . The non-volatile memory semiconductor device of  claim 8 , wherein the first trapping sub-layer comprises a composition of:
 at least one silicon nitride compound having a chemical formula of Si x N y  present in the range of about 50% to 100% on a atomic percentage basis; and   oxygen present in the range of about 0% to 50% on a atomic percentage basis.   
     
     
         14 . The non-volatile memory semiconductor device of  claim 8 , wherein the second trapping sub-layer comprises a silicon-rich silicon nitride compound containing more silicon on a atomic percentage basis than is present in stoichiometric silicon nitride. 
     
     
         15 . The non-volatile memory semiconductor device of  claim 1 , wherein the charge trapping layer is a graded layer having a variable composition and a thickness in the range of about 1 nm to 20 nm, the charge trapping layer comprising nitrogen-rich Si x N y  adjacent to the tunnel layer and silicon-rich Si x N y  adjacent to the interface region. 
     
     
         16 . The non-volatile memory semiconductor device of  claim 1 , wherein the interface region comprises SiON and has a thickness in the range of about 1 nm to 5 nm. 
     
     
         17 . The non-volatile memory semiconductor device of  claim 1 , wherein the charge blocking layer comprises:
 a first blocking sub-layer comprising at least one compound selected from the group consisting of SiO 2  and SiON;   a second blocking sub-layer comprising at least one compound selected from the group consisting of Al 2 O 3 , MgO, SrO, BaO, TiO, Ta 2 O 5 , BaTiO 3 , BaZrO 3 , ZrO 2 , HfO 2 , Y 2 O 3 , ZrSiO 4 , HfSiO 4 , LaAlO 3  and Si x N y ; and   a third blocking sub-layer comprising at least one compound selected from the group consisting of SiO 2  and SiON.   
     
     
         18 . The non-volatile memory semiconductor device of  claim 17 , wherein the charge blocking layer further comprises at least:
 a fourth blocking sub-layer adjacent to the interface region, the fourth blocking sub-layer comprising at least one silicon nitride compound having a chemical formula of Si x N y ; and   a fifth blocking sub-layer adjacent to the control gate, the fifth blocking sub-layer comprising at least one silicon nitride compound having a chemical formula of Si x N y .   
     
     
         19 . The non-volatile memory semiconductor device of  claim 1 , wherein the charge blocking layer has a thickness in the range of about 10 nm to 15 nm. 
     
     
         20 . A method of forming a gate stack on a semiconductor substrate having a channel comprising:
 depositing a tunnel layer over the channel;   depositing a charge trapping layer comprising a compound including silicon and nitrogen on top of the tunnel layer;   depositing a charge blocking layer containing an oxide of a charge blocking component on top of an interface region;   forming the interface region between the charge trapping layer and the charge blocking layer, the interface region comprising a compound including silicon, nitrogen and the charge blocking component; and   placing a control gate on top of the charge blocking layer.   
     
     
         21 . The method of forming a gate stack of  claim 20 , wherein depositing a tunnel layer over the channel comprises:
 depositing a first tunnel sub-layer over the channel, the first tunnel sub-layer comprising at least one component selected from the group consisting of SiO 2  and SiON;   depositing a second tunnel sub-layer on top of the first tunnel sub-layer, the second tunnel sub-layer comprising at least one component selected from the group consisting of Al 2 O 3 , MgO, SrO, BaO, TiO, Ta 2 O 5 , BaTiO 3 , BaZrO 3 , ZrO 2 , HfO 2 , Y 2 O 3 , ZrSiO 4 , HfSiO 4 , LaAlO 3  and Si x N y ; and   depositing a third tunnel sub-layer on top of the second tunnel sub-layer, the third tunnel sub-layer comprising at least one component selected from the group consisting of SiO 2  and SiON.   
     
     
         22 . The method of forming a gate stack of  claim 20 , wherein depositing a charge trapping layer comprises:
 depositing a first trapping sub-layer in a first chamber without air exposure, the first trapping sub-layer adjacent to the tunnel layer; and   depositing a second trapping sub-layer in the first chamber without air exposure, the second trapping sub-layer adjacent to the interface region.   
     
     
         23 . The method of forming a gate stack of  claim 22 , wherein forming the interface region comprises one or more of controlled oxidation of the second trapping sub-layer, oxidizing the second trapping sub-layer by exposing the second trapping sub-layer to air, and depositing a discrete interface region on top of the charge trapping layer in the first chamber without air exposure. 
     
     
         24 . The method of  claim 23 , wherein controlled oxidation of the second trapping sub-layer comprises one or more of oxidizing the second trapping sub-layer using wet oxidation, oxidizing the second trapping sub-layer using dry oxidation, oxidizing the second trapping sub-layer using radical oxidation, oxidizing the second trapping sub-layer using plasma oxidation, and oxidizing the second trapping sub-layer using oxygen implantation. 
     
     
         25 . The method of forming a gate stack of  claim 23 , wherein the first trapping sub-layer, the second trapping sub-layer and the interface region are deposited in separate chambers without air exposure between depositions.