Memory access control device and method thereof

Abstract

A memory access control device and method is provided with a cache memory having a plurality of cache areas, each for storing image data of one macroblock, and a cache table having a plurality of table areas, corresponding to the plurality of cache areas, each for storing a scheduled access counter that counts the number of scheduled accesses to a corresponding cache area and an in-frame address of image data of one macroblock stored in the corresponding cache area. A data request processor receives a data request including specification of an in-frame occupation region of the requested image data from the image processor, determines target image data of at least one macroblock required to process requested image data based on the in-frame occupation region of the requested image data, acquires the target image data from the cache memory, processes the image data requested by the data request using the acquired image data, and outputs the processed image data to the image processor.

1 . A memory access control device connectable to an external memory storing image data for processing image data requested by an image processor, the memory access control device comprising:
 a cache memory having a plurality of cache areas, each for storing image data of one macroblock, wherein a plurality of predetermined number of macroblocks constitute one frame; and   a cache controller having a cache table and a data request processor,   wherein the cache table has a plurality of table areas, corresponding to the plurality of cache areas, each for storing at least a scheduled access counter that counts the number of scheduled accesses to a corresponding cache area and an in-frame address of image data of one macroblock stored in the corresponding cache area,   wherein the data request processor is programmed to:   receive a data request including specification of an in-frame occupation region of the requested image data from the image processor;   determine target image data of at least one macroblock required to process the requested image data according to the in-frame occupation region of the requested image data;   acquire the target image data from the cache memory; and   process the requested image data using the acquired image data and output the processed image data to the image processor,   wherein if the target image data is not stored in the cache memory, the data request processor is programmed to:   select one of the table areas having the scheduled access counter with a value of “0” as an update table area;   determine whether the cache area corresponding to the update table area is a destination of the target image data;   output a read request instructing transmission of the target image data from the external memory to the corresponding cache area; and   store the in-frame address of the target image data in the update table area and increase the scheduled access counter of the update table area by “1”,   wherein if the target image data is stored in the cache memory and the read request for the target image data has not been output, or if the read request for the target image data has been output, the data request processor is further programmed to increase the scheduled access counter of the table area storing the in-frame address of the target image data by “1”, and   wherein the data request processor is programmed to read the target image data of one macroblock required to process the requested image data from one cache area of the cache memory and decrease the scheduled access counter of the table area corresponding to the cache area by “1” when the read image data has been used to process the requested image data.   
     
     
         2 . The memory access control device according to  claim 1 , wherein:
 each of the plurality of table areas further stores a validity flag indicating validity or an invalidity flag indicating invalidity of the image data in the corresponding cache area, and   the data request processor is programmed to select the update table that does not store the validity flag and store the validity flag in the update table area when the target image data has been read from the external memory and stored in the corresponding cache area.   
     
     
         3 . The memory access control device according to  claim 1 , wherein the data request processor includes a Direct Memory Access (DMA) controller that implements DMA transmission of the target image data between the external memory module and the cache memory. 
     
     
         4 . The memory access control device according to  claim 1 , wherein:
 the image processor successively decodes image data for each frame and the external memory stores image data of a previous frame decoded by the image processor, and   the data request processor is programmed to receive the data request from the image processor requesting image data of the previous frame required to decode image data of a current frame, process the requested image data based on target image data read from the external memory through the cache memory, and output the processed image data to the image processor.   
     
     
         5 . A memory access control device connectable to an external memory storing image data for processing image data requested by an image processor, the memory access control device comprising:
 a cache memory having a plurality of cache areas, each for storing image data of one macroblock, wherein a plurality of predetermined number of macroblocks constitute one frame; and   a cache controller having a cache table and a data request processor,   wherein the cache table has a plurality of table areas, corresponding to the plurality of cache areas, each for storing a scheduled access counter that counts the number of scheduled accesses to a corresponding cache area, a validity flag indicating validity or an invalidity flag indicating invalidity of image data in the corresponding cache area, and an in-frame address of image data of one macroblock stored in the corresponding cache area,   wherein the data request processor is programmed to:   receive a data request including specification of an in-frame occupation region of the requested image data from the image processor;   determine target image data of at least one macroblock required to process the requested image data according to the in-frame occupation region of the requested image data;   acquire the target image data from the cache memory;   process the requested image data using the acquired image data and output the processed image data to the image processor,   wherein if any table area in the cache table does not store both the in-frame address of the target image data and the validity flag, and the scheduled access counter thereof does not have a value of “1” or more, the data request processor is programmed to:   select one of the table areas having the scheduled access counter with a value of “0” as an update table area;   the in-frame address of the target image data in the update table area;   increase the scheduled access counter of the update table area by “1”; and   output the read request instructing transmission of the target image data from the external memory to the cache area corresponding to the update table area,   wherein if any table area in the cache table stores the in-frame address of the target image data and either the validity flag or the scheduled access counter having a value of “1” or more, the data request processor is programmed to increase the scheduled access counter of that table area by “1”, and   wherein the data request processor is programmed to read image data of one macroblock required to process the requested image data from one cache area of the cache memory and decrease the scheduled access counter of the table area corresponding to the cache area by “1” when the read image data has been used to process the requested image data.   
     
     
         6 . The memory access control device according to  claim 5 , wherein the data request processor includes a Direct Memory Access (DMA) controller that implements DMA transmission of the target image data between the external memory module and the cache memory. 
     
     
         7 . The memory access control device according to  claim 5 , wherein:
 the image processor successively decodes image data for each frame and the external memory stores image data of a previous frame decoded by the image processor, and   the data request processor is programmed to receive the data request from the image processor requesting image data of the previous frame required to decode image data of a current frame, process the requested image data based on target image data read from the external memory through the cache memory, and output the programmed image data to the image processor.   
     
     
         8 . A method of controlling memory access for a memory access control device that is connectable to an external memory storing image data for processing image data requested by an image processor, the memory access control device having a cache memory having a plurality of cache areas, each for storing image data of one macroblock, wherein a plurality of predetermined number of macroblocks constitute one frame, and a cache controller having a cache table and a data request processor, wherein the cache table has a plurality of table areas, corresponding to the plurality of cache areas, each for storing at least a scheduled access counter that counts the number of scheduled accesses to a corresponding cache area and an in-frame address of image data of one macroblock stored in the corresponding cache area, the method, which is executed by the data request processor, comprising the steps of:
 receiving a data request including specification of an in-frame occupation region of the requested image data from the image processor;   determining target image data of at least one macroblock required to process the requested image data according to the in-frame occupation region of the requested image data;   acquiring the target image data from the cache memory;   processing the requested image data using the acquired image data and outputting the processed image data to the image processor,   wherein if the target image data is not stored in the cache memory, the method comprises the steps of:   selecting one of the table areas having the scheduled access counter with a value of “0” as an update table area;   determining whether the cache area corresponding to the update table area is a destination of the target image data;   outputting a read request instructing transmission of the target image data from the external memory to the corresponding cache area; and   storing the in-frame address of the target image data in the update table area, and increasing the scheduled access counter of the update table area by “1”,   wherein if the target image data is stored in the cache memory and the read request for the target image data has not been output, or if the read request for the target image data has been output, increasing the scheduled access counter of the table area that stores the in-frame address of the target image data by “1”,   wherein when the read image data has been used to process the requested image data, reading the target image data of one macroblock required to process the requested image data from one cache area of the cache memory and decreasing the scheduled access counter of the table area corresponding to the cache area by “1”.