Semiconductor devices and methods of fabricating the same

Abstract

A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

1 - 20 . (canceled) 
     
     
         21 . A flash memory device, comprising:
 an active region including a main surface and a pair of recess regions of which a bottom surface is lower than the main surface, the pair of recess regions disposed in the active region, and separated from each other by a predetermined distance;   a ground selection gate line and a string selection gate line crossing over the respective recess regions; and   at the least one of a word line crossing over the main surface of the active region between the ground selection gate line and the string selection gate line.   
     
     
         22 . The flash memory device as claimed in  claim 21 , wherein a charge trapping layer is interposed between the word line and the active region, and between the active region and a selection gate line including the ground selection gate line and the string selection gate line. 
     
     
         23 . The flash memory device as claimed in  claim 21 , wherein a charge trapping layer is interposed between the word line and the active region, and a gate insulating layer is interposed between the active region and a selection gate line including the ground selection gate line and the string selection gate line. 
     
     
         24 . The flash memory device as claimed in  claim 21 , further comprising a tunnel insulating layer, a charge trapping layer and a blocking insulating layer, which are sequentially stacked between the word line and the active region,
 wherein the word line disposed over the blocking insulating layer includes a metallic material having a work function of about 4.5 eV or greater.   
     
     
         25 . The flash memory device as claimed in  claim 21 , wherein the word line comprises:
 a floating gate on the active region;   a control gate electrode formed on the floating gate, and crossing over the active region; and   an intergate dielectric layer interposed between the floating gate and the control gate electrode,   wherein a tunnel insulating layer is interposed between the floating gate and the active region.   
     
     
         26 . The flash memory device as claimed in  claim 21 , wherein the ground selection gate line and the string selection gate line comprise:
 a lower selection gate;   an upper selection gate on the lower selection gate; and   an intergate insulating layer interposed between the lower selection gate and the upper selection gate,   the gate insulating layer being interposed between the lower selection gate and the active region, and the lower selection gate and the upper selection gate being electrically connected to each other.   
     
     
         27 . The flash memory device as claimed in  claim 21 , wherein widths of the ground selection and the string selection gate line are greater than that of the recess regions. 
     
     
         28 . The flash memory device as claimed in  claim 27 , wherein the ground selection gate line and the string selection gate line cover the active region at either side of the respective pair of recess regions.