System for multi-byte reading

Abstract

A control device, system and method for multi-pixel reading provides a processor receiving multi-pixel, uses memory units wherein each memory unit sequentially receiving a writing enable signal, and then receiving and storing multi-pixel. Simultaneously, the processor having multi-data bus receives multi-pixel of the each memory unit output. The clock of the enabling all the memory units is less than the delay of the processor reading, so that reducing the spare time of the image decoding system and reducing the reading time of the reading image.

1 . A controlling system for outputting multi-byte image data, comprising:
 an inverse discrete cosine transform (IDCT) unit for processing a plurality of image data;   a plurality of buffers for receiving said plurality of image data processed by said inverse discrete cosine transform (IDCT) unit;   a multiplexer connected to said plurality of buffers;   a control circuit connected to said multiplexer for utilizing said multiplexer to move said image data from said buffers to said control circuit; and   a processor, connected to said control circuit, for receiving said image data from said control circuit simultaneously.   
     
     
         2 . The controlling system according to  claim 1 , further comprising a data bus for transmitting data from said control circuit to said processor, wherein the bit number of said data bus is not less than the total bit number of said buffers. 
     
     
         3 . The controlling system according to  claim 1 , when said processor is being idle, said buffers transmit said plurality of image data through said multiplexer to said control circuit, and when said processor is reading, said processor reads a plurality of said image data from said control circuit directly. 
     
     
         4 . The controlling system according to  claim 1 , wherein said multiplexer controls said image data transmitted between said buffers and said control circuit, and at the same time, only one said buffer transmits data to said control circuit and other said buffers receive said image data processed by said inverse discrete cosine transform (IDCT) unit. 
     
     
         5 . The controlling system according to  claim 1 , when any said buffer is full of data, said control circuit moves data of said filled buffer to said control circuit for enabling said buffer to receive data from said inverse discrete cosine transform (IDCT) unit. 
     
     
         6 . The controlling system according to  claim 1 , when said control circuit is full of data, said IDCT unit sends a signal to said processor for informing said processor to read said control circuit. 
     
     
         7 . A controlling system for outputting multi-byte image data, comprising:
 an inverse discrete cosine transform (IDCT) unit for processing a plurality of image data;   a plurality of buffers for receiving said plurality of image data processed by said inverse discrete cosine transform (IDCT) unit;   a multiplexer connected to said plurality of buffers;   a control circuit connected to said multiplexer for utilizing said multiplexer to move said image data from said buffers to said control circuit and including:
 a plurality of memory units, each said memory unit receiving and storing a plurality of bit image data, wherein said plurality of memory units simultaneously and correspondingly output said plurality of bit image data, and the sum of said plurality of said bit image data equal to a plurality of byte image data; and 
 a plurality of control signal units for generating a plurality of writing enable signals, said plurality of writing enable signals being corresponding to said plurality of memory units, respectively, wherein said plurality of writing enable signals control said plurality of memory units to be stored in said plurality of bit image data in sequence; and 
   a processor, connected to said control circuit, for receiving said image data from said control circuit simultaneously.