Method for testing semiconductor memory device using probe and semiconductor memory device using the same

Abstract

Example embodiments relate to a semiconductor memory device including a first pad having a probe region and a sensing region, the first pad may be adapted to come in contact with a primary probe, a sensing unit adapted to sense a weak contact of the first pad and the primary probe, the sensing unit may generate an output current in response to a contact point of the primary probe, and a second pad may be adapted to come in contact with a secondary probe to input/output an electric signal. The output current of the sensing unit may be output through the second pad or the secondary probe.

1 . A semiconductor memory device, comprising:
 a first pad having a probe region and a sensing region, the first pad adapted to come in contact with a primary probe;   a sensing unit adapted to sense a weak contact of the first pad and the primary probe, the sensing unit generating an output current in response to a contact point of the primary probe; and   a second pad adapted to come in contact with a secondary probe to input/output an electric signal,   wherein the output current of the sensing unit is output through the second pad or the secondary probe.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the sensing unit generates the output current in response to a first voltage corresponding to a voltage obtained by dividing a power supply voltage using a resistance component, generated in response to a contact point of the primary probe, and a plurality of resistors. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the sensing unit comprises:
 a voltage matching unit adapted to output a voltage in response to a contact point of the primary probe; and   a current generator adapted to generate the output current corresponding to the output voltage of the voltage matching unit.   
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the voltage output from the voltage matching unit corresponds to a voltage obtained by dividing a power supply voltage using a resistance component, generated in response to the contact point of the primary probe, and a plurality of resistors. 
     
     
         5 . The semiconductor memory device of  claim 3 , wherein the voltage matching unit comprises:
 a plurality of resistors;   a comparator adapted to compare a voltage obtained by dividing a power supply voltage using a resistance component, generated in response to the contact point of the primary probe, and a plurality of resistors to the output voltage of the voltage matching unit; and   a transistor having a gate adapted to receive the output signal of the comparator, a first terminal to which the power supply voltage is applied, and a second terminal connected to a source of the ground voltage and an output terminal of the voltage matching unit.   
     
     
         6 . The semiconductor memory device of  claim 3 , wherein the current generator includes a transistor having a gate adapted to receive the output voltage of the voltage matching unit, a first terminal to which the power supply voltage is applied, and a second terminal connected to the second pad. 
     
     
         7 . The semiconductor memory device of  claim 1 , further comprising a controller adapted to control operation of the sensing unit in response to a test signal. 
     
     
         8 . The semiconductor memory device of  claim 7 , wherein the controller includes a transistor having a gate receiving the test signal, a first terminal receiving the power supply voltage, and a second terminal connected to the output terminal of the voltage matching unit and an input terminal of the current generator. 
     
     
         9 . The semiconductor memory device of  claim 1 , wherein the first pad is a sensor pad. 
     
     
         10 . The semiconductor memory device of  claim 1 , wherein a ground voltage is applied to the primary probe. 
     
     
         11 . The semiconductor memory device of  claim 1 , wherein the sensing unit compares a first voltage generated according to a resistance component in response to the contact point of the primary probe and a plurality of variable resistors, to a reference voltage, and generates an output current having a first logic state or a second logic state. 
     
     
         12 . The semiconductor memory device of  claim 11 , wherein the first voltage corresponds to a voltage obtained by dividing a power supply voltage using the resistance component generated in response to the contact point of the primary probe and the plurality of variable resistors. 
     
     
         13 . The semiconductor memory device of  claim 11 , wherein the sensing unit comprises:
 a voltage matching unit adapted to compare the first voltage to the reference voltage and outputting a voltage having a first logic state or a second logic state; and   a current generator adapted to generate the output current having the first logic state or the second logic state in response to the output voltage of the voltage matching unit.   
     
     
         14 . The semiconductor memory device of  claim 13 , wherein the voltage matching unit comprises:
 a plurality of variable resistors;   a comparator adapted to compare the first voltage to the reference voltage.   
     
     
         15 . The semiconductor memory device of  claim 14 , wherein the voltage matching unit further comprises an inverter inverting an output signal of the comparator. 
     
     
         16 . A method for testing probe contact with a semiconductor memory device having a plurality of pads, comprising:
 applying a voltage to a primary probe coming into contact with a first pad;   generating an output current in response to a contact point of the primary probe;   outputting the output current through a second pad or a secondary probe coming into contact with the second pad; and   determining whether a weak contact exists between the primary probe and the first pad based on the output current.   
     
     
         17 . The method of  claim 16 , wherein generating of the output current comprises:
 generating a voltage corresponding to the contact point of the primary probe; and   generating the output current corresponding to the generated voltage.   
     
     
         18 . The method of  claim 17 , wherein generating of the voltage comprises dividing a power supply voltage according to a resistance component generated in response to the contact point of the primary probe and a plurality of resistors. 
     
     
         19 . The method of  claim 17 , wherein generating of the output current includes applying the generated voltage to a gate of a transistor that generates the output current. 
     
     
         20 . The method of  claim 16 , wherein determining whether the weak contact exists comprises determining that the primary probe is in a weak contact with the first pad when the output current is greater than a threshold value. 
     
     
         21 - 25 . (canceled)