Semiconductor device with double-sided electrode structure and its manufacturing method

Abstract

According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.

1 . A semiconductor device, comprising:
 a multilayer substrate having a plurality of package substrates and first and second wirings therein;   an LSI chip mounted on a front-side surface of the multilayer substrate, wherein the LSI chip is electrically connected to the first and second wirings;   a sealing resin which covers the LSI chip on the multilayer substrate;   a plurality of metallic pads formed on the front-side surface of the multilayer substrate and around the sealing resin, wherein at least one of the metallic pads is electrically connected to the first wiring; and   a plurality of back-face electrodes formed on a backside surface of the multilayer substrate, wherein at least one of the electrodes is electrically connected to the second wiring.   
     
     
         2 . A semiconductor device in accordance with  claim 1 , further comprising a bonding wire connecting the LSI chip and the multilayer substrate, wherein the bonding wire is covered with the sealing resin. 
     
     
         3 . A semiconductor device in accordance with  claim 1 , wherein the multilayer substrate has a recess portion in which the LSI chip is disposed. 
     
     
         4 . A semiconductor device in accordance with  claim 1 , wherein the multilayer substrate has a via hole therein and the one of the metallic pads is electrically connected to the first wiring through a conductive member in the via hole. 
     
     
         5 . A semiconductor device in accordance with  claim 1 , wherein the multilayer substrate has a via hole therein and the one of the electrodes is electrically connected to the second wiring through a conductive member in the via hole. 
     
     
         6 . A semiconductor device in accordance with  claim 1 , further comprising another LSI chip mounted on the front-side surface of the multilayer substrate, wherein the another LSI chip is covered with the sealing resin. 
     
     
         7 . A semiconductor device in accordance with  claim 1 , wherein the LSI chip has a main surface in which an LSI circuit is formed, said LSI chip being mounted on the front-side surface of the multilayer substrate with the main surface of the LSI chip facing the front-side surface of the multilayer substrate. 
     
     
         8 . A semiconductor device, comprising:
 a multilayer substrate having a plurality of package substrates and first and second wirings therein, said multilayer substrate having a front-side surface;   an LSI chip mounted on said front-side surface of the multilayer substrate, wherein the LSI chip is electrically connected to the first and second wirings;   a sealing resin which covers the LSI chip on the multilayer substrate;   a plurality of metallic pads provided on at least a portion of said front-side surface of the multilayer substrate, said plurality of metallic pads being arranged about said sealing resin, wherein at least one of the metallic pads is electrically connected to the first wiring; and   a plurality of back-face electrodes formed on a backside surface of the multilayer substrate, wherein at least one of the electrodes is electrically connected to the second wiring.   
     
     
         9 . A semiconductor device in accordance with  claim 8 , further comprising a bonding wire connecting the LSI chip and the multilayer substrate, wherein the bonding wire is covered with the sealing resin. 
     
     
         10 . A semiconductor device in accordance with  claim 8 , wherein at least a portion of said front-side surface defines a recessed portion, said LSI chip being disposed in said recessed portion. 
     
     
         11 . A semiconductor device in accordance with  claim 8 , wherein the multilayer substrate has a via hole therein and the one of the metallic pads is electrically connected to the first wiring through a conductive member in the via hole. 
     
     
         12 . A semiconductor device in accordance with  claim 8 , wherein the multilayer substrate has a via hole therein and the one of the electrodes is electrically connected to the second wiring through a conductive member in the via hole. 
     
     
         13 . A semiconductor device in accordance with  claim 8 , further comprising another LSI chip mounted on the front-side surface of the multilayer substrate, wherein the another LSI chip is covered with the sealing resin. 
     
     
         14 . A semiconductor device in accordance with  claim 8 , wherein the LSI chip has a main surface in which an LSI circuit is formed, said LSI chip being mounted on the front-side surface of the multilayer substrate with the main surface of the LSI chip facing the front-side surface of the multilayer substrate. 
     
     
         15 . A semiconductor device, comprising:
 a multilayer substrate having a plurality of package substrates and first and second wirings therein, said multilayer substrate having a front-side surface;   an LSI chip mounted on said front-side surface of the multilayer substrate, wherein the LSI chip is electrically connected to the first and second wirings;   a sealing resin which covers the LSI chip on the multilayer substrate, at least a portion of said sealing resin engaging said front-side surface;   a plurality of metallic pads provided on at least a portion of said front-side surface of the multilayer substrate, said plurality of metallic pads being arranged about said sealing resin, wherein at least one of the metallic pads is electrically connected to the first wiring;   a plurality of back-face electrodes formed on a backside surface of the multilayer substrate, wherein at least one of the electrodes is electrically connected to the second wiring.   
     
     
         16 . A semiconductor device in accordance with  claim 15 , further comprising a bonding wire connecting the LSI chip and the multilayer substrate, wherein the bonding wire is covered with the sealing resin. 
     
     
         17 . A semiconductor device in accordance with  claim 15 , wherein at least a portion of said front-side surface defines a recessed portion, said LSI chip being disposed in said recessed portion. 
     
     
         18 . A semiconductor device in accordance with  claim 15 , wherein the multilayer substrate has a via hole therein and the one of the metallic pads is electrically connected to the first wiring through a conductive member in the via hole. 
     
     
         19 . A semiconductor device in accordance with  claim 15 , wherein the multilayer substrate has a via hole therein and the one of the electrodes is electrically connected to the second wiring through a conductive member in the via hole. 
     
     
         20 . A semiconductor device in accordance with  claim 15 , further comprising another LSI chip mounted on the front-side surface of the multilayer substrate, wherein the another LSI chip is covered with the sealing resin.