US2011089525A1PendingUtilityA1

Manufacturing method for semiconductor device and semiconductor device

Assignee: TOSHIBA KKPriority: Jan 28, 2008Filed: Dec 16, 2010Published: Apr 21, 2011
Est. expiryJan 28, 2028(~1.5 yrs left)· nominal 20-yr term from priority
H10W 10/17H10W 10/014H10D 84/0151H10D 30/60H10D 84/038
44
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Claims

Abstract

A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.

Claims

exact text as granted — not AI-modified
1 .- 15 . (canceled) 
     
     
         16 . A semiconductor device comprising:
 an active area formed on a semiconductor substrate and   a STI isolating the active area, the STI having an upper face protruding to a height of 22 to 50 nm from a surface of the semiconductor substrate, and the STI having a taper of a minimum taper angle of 90° or more on a side face of STI.   
     
     
         17 . The semiconductor device according to  claim 16 , wherein the STI protrudes to a height of 30 to 50 nm from the surface of the semiconductor substrate. 
     
     
         18 . The semiconductor device according to  claim 16 , wherein the STI includes a TEOS film. 
     
     
         19 . The semiconductor device according to  claim 16 , wherein a gate electrode and a side wall of the gate electrode are formed in the active area. 
     
     
         20 . The semiconductor device according to  claim 16 , wherein an end portion of the taper in contact with the semiconductor substrate is depressed from a surface of the semiconductor substrate.

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