Semiconductor memory apparatus and data input/output method thereof

Abstract

A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.

1 . A semiconductor memory apparatus comprising:
 a first bit line of a first memory bank;   a first middle input/output line electrically connected to the first bit line;   a second bit line of a second memory bank;   a second middle input/output line electrically connected to the second bit line; and   a shared local input/output line selectively electrically connected to each of the first and second middle input/output lines,   wherein a bank selection signals control the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.   
     
     
         2 . The semiconductor memory apparatus of  claim 1 , wherein the first middle input/output line is electrically connected to the first bit line and the second middle input/output line is electrically connected to the second bit line in response to a column selection signal, such that the first middle input/output line is electrically connected to the first bit line and the second middle input/output line is electrically connected to the second bit line simultaneously. 
     
     
         3 . The semiconductor memory apparatus of  claim 2 , wherein the interval during which the first middle input/output line is electrically connected to the shared local input/output line does not overlapped with the interval during which the second middle input/output line is electrically connected to the shared local input/output line. 
     
     
         4 . The semiconductor memory apparatus of  claim 1 , wherein the bank selection signal includes information indicating which one of the first and second memory banks is associated with a data read/write operation. 
     
     
         5 . The semiconductor memory apparatus of  claim 1 , further comprising a control unit generating the one or more bank selection signals in response to a read/write command and a bank address signal. 
     
     
         6 . The semiconductor memory apparatus of  claim 2 , wherein the bank selection signal is configured to be enabled earlier than the column selection signal, and to be disabled later than the column selection signal. 
     
     
         7 . A semiconductor memory apparatus comprising:
 a shared column decoding unit configured to simultaneously enable a column selection line of the first and second memory banks in response to a column address signal and a main strobe signal;   an input/output switching unit configured to selectively electrically connect the first and second memory banks to a shared local input/output line in response to a bank selection signal; and   a shared input/output driving unit configured to amplify data transferred via the shared local input/output line and transfer the amplified data onto a global input/output line in a data read operation, and to amplify data transferred via the global input/output line and transfer the amplified data onto the shared local input/output line in a data write operation, in response to the main strobe signal.   
     
     
         8 . The semiconductor memory apparatus of  claim 7 , wherein the bank selection signal includes information indicating which one of the first and second memory banks is associated with the data read/write operation. 
     
     
         9 . The semiconductor memory apparatus of  claim 7 , wherein the main strobe signal includes information on the data read or data write operation of the first and second memory banks. 
     
     
         10 . The semiconductor memory apparatus of  claim 7 , wherein the semiconductor memory apparatus further includes a control unit configured to generate the bank selection signal and the main strobe signal in response to a read/write command and a bank address signal. 
     
     
         11 . The semiconductor memory apparatus of  claim 7 , wherein the bank selection signal is configured to be enabled earlier than a column selection signal, and to be disabled later than the column selection signal. 
     
     
         12 . A semiconductor memory apparatus comprising:
 a first memory bank;   a second memory bank;   first and second middle input/output lines configured to communicate with the first and second memory banks respectively, in response to a column selection signal; and   a shared local input/output line selectively electrically connected to the first and second middle input/output lines,   wherein the column selection signal simultaneously enables communication of the first and second middle input/output lines with the first and second memory banks , and the electrical connection between the shared local input/output line and the first memory bank and the electrical connection between the shared local input/output line and the second memory bank are made selectively in response to a bank selection signal.   
     
     
         13 . The semiconductor memory apparatus of  claim 12 , further comprising a column selection switching unit configured to transfer data stored in the first memory bank onto the first middle input/output line in a data read operation and transfer data transferred via the first middle input/output line to the first memory bank in a data write operation, when the column selection signal is enabled. 
     
     
         14 . The semiconductor memory apparatus of  claim 12 , further comprising a column selection switching unit configured to transfer data stored in the second memory bank onto the second middle input/output line in a data read operation and transfer data transferred via the second middle input/output line to the second memory bank in a data write operation, when the column selection signal is enabled. 
     
     
         15 . The semiconductor memory apparatus of  claim 12 , wherein the bank selection signal includes information indicating which one of the first and second memory banks is associated with a data read/write operation. 
     
     
         16 . The semiconductor memory apparatus of  claim 12 , further comprising a shared input/output driving unit configured to amplify data transferred via the shared local input/output line and transfer the amplified data onto a global input/output line in a data read operation, and to amplify data transferred via the global input/output line and transfer the amplified data onto the shared local input/output line in a data write operation, in response to a main strobe signal. 
     
     
         17 . The semiconductor memory apparatus of  claim 16 , further comprising a control unit configured to generate the bank selection signal and the main strobe signal in response to a read/write command and a bank address signal. 
     
     
         18 . A data input/output method of a semiconductor memory apparatus comprising first and second memory banks and a local input/output line shared by the first and second memory banks, the data input/output method comprising:
 enabling a column selection signal of the first memory bank and the second memory bank when a data read/write operation is performed on the first memory bank and also when a data read/write operation is performed on the second memory bank; and   electrically connecting only one of the first and second memory banks to the shared local input/output line depending upon on which of the first and second memory banks a data read/write operation is to be performed.   
     
     
         19 . The data input/output method of  claim 18 , wherein the column selection signal of the first memory bank and the second memory bank is enabled in response to a main strobe signal and a column address signal. 
     
     
         20 . The data input/output method of  claim 19 , wherein the main strobe signal includes information on the data read/write operation of the first and second memory banks. 
     
     
         21 . The data input/output method of  claim 18 , wherein electrically connecting only one of the first and second memory banks to the shared local input/output line is performed in response to a bank selection signal including information on which one of the first and second memory banks is associated with the data read/write operation. 
     
     
         22 . The data input/output method of  claim 19 , wherein the data input/output method further comprises enabling a shared input/output driving unit coupled to the shared local input/output line in response to the main strobe signal when the data read/write operation is performed on the first memory bank and when the data read/write operation is performed on the second memory bank. 
     
     
         23 . The data input/output method of  claim 22 , further comprising:
 amplifying, by the shared input/output driving unit, data transferred via the shared local input/output line and transferring, by the shared input/output driving unit, the amplified data onto a global input/output line in the data read operation, in response to the main strobe signal; and   amplifying, by the shared input/output driving unit, data transferred via the global input/output line and transferring, by the shared input/output driving unit the amplified data onto the shared local input/output line in the data write operation, in response to the main strobe signal.