Method to improve ferroelectric memory performance and reliability

Abstract

One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.

1 . A ferroelectric random access memory (FRAM) array, comprising:
 a plurality of electrically conducive bit lines;   a plurality of electrically conducive plate lines, wherein the plurality of electrically conducive plate lines are substantially perpendicular to the plurality of electrically conducive bit lines;   a plurality of electrically conducive word lines, wherein the plurality of electrically conducive word lines are substantially perpendicular to the plurality of electrically conducive bit lines;   a plurality of transistors electrically coupled to the plurality of plate lines and the word lines;   at least one reference voltage source coupled to the plurality of electrically conducive bit lines;   a plurality of sense amplifiers coupled to the plurality of electrically conducive bit lines and to the at least one reference voltage source;   a plurality of ferroelectric capacitors coupled to the plurality of plate lines and to the plurality of plurality of transistors, wherein the plurality of ferroelectric capacitors store a plurality of data states; and   a control circuit coupled to the plurality of ferroelectric capacitors, wherein the control circuit writes the plurality of ferroelectric capacitors to a preferred data state after all high temperature processes have been completed and before packaging of the FRAM memory array.   
     
     
         2 . The FRAM memory array of  claim 1  wherein the preferred data state is a high data state. 
     
     
         3 . A ferroelectric random access memory (FRAM) memory array, comprising:
 a plurality of electrically conductive bit lines;   a plurality of electrically conductive plate lines, wherein the plurality of electrically conductive plate lines are substantially perpendicular to the plurality of electrically conductive bit lines;   a plurality of electrically conductive word lines, wherein the plurality of electrically conductive word lines are substantially perpendicular to the plurality of electrically conductive bit lines;   a plurality of transistors electrically coupled to the plurality of plate lines and the word lines;   at least one reference voltage source coupled to the plurality of electrically conductive bit lines;   a plurality of sense amplifiers coupled to the plurality of electrically conducive bit lines and to the at least one reference voltage source;   a plurality of ferroelectric capacitors coupled to the plurality of plate lines and to the plurality of plurality of transistors, wherein the plurality of ferroelectric capacitors store a plurality of data states; and   a control circuit coupled to the plurality of ferroelectric capacitors, wherein the control circuit writes the plurality of ferroelectric capacitors to a preferred data state during a final test of the FRAM memory array in packaged form.   
     
     
         4 . The FRAM memory array of  claim 4  wherein the preferred data state is a high data state.