Semiconductor device

Abstract

One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit.

1 . A semiconductor device comprising:
 a first semiconductor chip that includes a driver circuit;   a second semiconductor chip that includes a receiver circuit and an external terminal; and   a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip, wherein   the first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, and   the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to anyone of the through silicon vias and the external terminal.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein
 the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and   the input switching circuit activates any one of the tri-state inverters.   
     
     
         3 . The semiconductor device as claimed in  claim 1 , wherein
 the input switching circuit includes a primary selection circuit that activates a first tri-state inverter that is inserted between the external terminal and the receiver circuit, and a secondary selection circuit that activates one of second tri-state inverters each of which is inserted between an associated one of the through silicon vias and the receiver circuit, and   the secondary selection circuit inactivates all of the second tri-state inverters when the primary selection circuit activates the first tri-state inverter.   
     
     
         4 . The semiconductor device as claimed in  claim 3 , wherein the secondary selection circuit activates any one of the second tri-state inverters based on a selection signal when the primary selection circuit inactivates the first tri-state inverter. 
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein
 the first semiconductor chip includes 1 st  to n th  driver circuits,   the second semiconductor chip includes 1 st  to n th  receiver circuits,   the plurality of through silicon vias includes 1 st  to n+m th  through silicon vias,   the output switching circuit selectively connects each of the 1 st  to n th  driver circuits to different ones of the 1 st  to n+m th  through silicon vias by connecting an output terminal of an i th  driver circuit to one of i th  to i+m th  through silicon vias, where i is an integer among 1 to n, and   the input switching circuit selectively connects each of the 1 st  to n th  receiver circuits to different ones of the 1 st  to n+m th  through silicon vias by connecting an input terminal of an i th  receiver circuit to one of i th  to i+m th  through silicon vias.   
     
     
         6 . The semiconductor device as claimed in  claim 5 , wherein at least one of the through silicon vias that is connected to neither the driver circuit nor the receiver circuit is defective. 
     
     
         7 . The semiconductor device as claimed in  claim 5 , wherein the first semiconductor chip and a plurality of the second semiconductor chips are laminated, and the through silicon vias are arranged on the second semiconductor chips. 
     
     
         8 . The semiconductor device as claimed in  claim 7 , wherein the through silicon vias assigned a same number that are arranged on the second semiconductor chips are all short-circuited. 
     
     
         9 . The semiconductor device as claimed in  claim 8 , wherein a connection relation between the driver circuits and the through silicon vias and a connection relation between the receiver circuits and the through silicon vias are same in the second semiconductor chips. 
     
     
         10 . The semiconductor device as claimed in  claim 5 , wherein a plurality of the first semiconductor chips and the second semiconductor chip are laminated, and the through silicon vias are arranged on the first semiconductor chips. 
     
     
         11 . The semiconductor device as claimed in  claim 10 , wherein the through silicon vias assigned a same number that are arranged on the first semiconductor chips are all short-circuited. 
     
     
         12 . The semiconductor device as claimed in  claim 11 , wherein a connection relation between the driver circuits and the through silicon vias and a connection relation between the receiver circuits and the through silicon vias are same in the first semiconductor chips. 
     
     
         13 . The semiconductor device as claimed in  claim 1 , wherein one of the first and second semiconductor chips is an interface chip and the other is a core chip.