Integrated circuit including four layers of vertically stacked embedded re-writeable non-volatile two-terminal memory

Abstract

A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.

1 . An integrated circuit with embedded non-volatile re-writeable two-terminal memory, comprising:
 a semiconductor substrate including front end of line (FEOL) active circuitry fabricated on the substrate; and   four layers of memory integrally fabricated above and in direct contact with the substrate such that the four layers of memory are vertically stacked upon one another and over the substrate, each layer of memory including at least one two-terminal cross-point memory array embedded in the layer, each two-terminal cross-point memory array including a plurality of non-volatile re-writeable two-terminal memory elements,   each two-terminal memory element comprises a crystalline conductive metal oxide that is electrically in series with and is positioned at an intersection of only one of a plurality of first conductive array lines and only one of a plurality of second conductive array lines in its respective two-terminal cross-point memory array,   each two-terminal memory element is configured to store data as a plurality of conductivity profiles that are retained in the absence of electrical power and can be non-destructively determined by applying a read voltage across its respective first and second conductive array lines, and the data can be reversibly switched between the plurality of conductivity profiles by applying a write voltage having a predetermined magnitude and polarity across its respective first and second conductive array lines, and wherein at least a portion of the FEOL active circuitry is electrically coupled with the plurality of first and second conductive array lines in each layer and is configured to apply to at least one two-terminal memory element in at least one of the four layers in response to at least one signal, the read voltage during a read operation and the write voltage during a write operation.   
     
     
         2 . The integrated circuit of  claim 1 , wherein each two-terminal memory element further comprises a non-ohmic device electrically in series with the memory element and its respective first and second conductive array lines. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the crystalline conductive metal oxide comprises a perovskite. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the perovskite comprises a single crystalline structure. 
     
     
         5 . The integrated circuit of  claim 3 , wherein the perovskite comprises a polycrystalline structure. 
     
     
         6 . The integrated circuit of  claim 1 , wherein crystalline conductive metal oxide comprises a single crystalline structure. 
     
     
         7 . The integrated circuit of  claim 1 , wherein crystalline conductive metal oxide comprises a polycrystalline structure. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the plurality of first and second conductive array lines in each layer are electrically isolated from the plurality of first and second conductive array lines in an adjacent layer. 
     
     
         9 . The integrated circuit of  claim 1 , wherein the plurality of two-terminal memory elements in one of the layers shares at least one of its conductive array lines with the plurality of two-terminal memory elements in an adjacent layer. 
     
     
         10 . The integrated circuit of  claim 1 , wherein applying the read voltage across the two-terminal memory element generates a read current through the two-terminal memory element and a magnitude of the read current is indicative of the data stored in the two-terminal memory element. 
     
     
         11 . The integrated circuit of  claim 1 , wherein the at least one signal includes an address signal. 
     
     
         12 . The integrated circuit of  claim 1 , wherein the four layers of memory have a first footprint and the FEOL active circuitry has a second footprint that is less than or equal to the first footprint. 
     
     
         13 . The integrated circuit of  claim 1 , wherein the semiconductor substrate comprises a silicon wafer. 
     
     
         14 . The integrated circuit of  claim 13 , wherein the FEOL active circuitry comprises CMOS circuitry. 
     
     
         15 . The integrated circuit of  claim 1 , wherein each two-terminal memory element includes a first terminal electrically coupled with its respective first conductive array line and a second terminal electrically coupled with its respective second conductive array line. 
     
     
         16 . The integrated circuit of  claim 15 , wherein each two-terminal memory element is disposed in a two-terminal memory cell. 
     
     
         17 . The integrated circuit of  claim 1 , wherein the plurality of conductivity profiles store exactly one bit of data. 
     
     
         18 . The integrated circuit of  claim 1 , wherein the plurality of conductivity profiles store more than one bit of data. 
     
     
         19 . The integrated circuit of  claim 18 , wherein the plurality of conductivity profiles store exactly two bits of data. 
     
     
         20 . The integrated circuit of  claim 1 , wherein the write operation on the at least one two-terminal memory element does not require an erase operation that directly precedes the write operation. 
     
     
         21 . The integrated circuit of  claim 1 , wherein a subsequent write operation is not necessary after the read operation.