Non-volatile memory device

Abstract

A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

1 . A non-volatile memory device comprising:
 a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate;   a gate structure on the surface of the active region; and   source/drain regions in the active region at opposite sides of the gate structure, the source/drain regions respectively comprising a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region, the first impurity region having a doping concentration that is greater than that of the second impurity regions.   
     
     
         2 . The non-volatile memory device of  claim 1 , wherein the doping concentration of the first impurity region is at least two times greater than that of the second impurity regions. 
     
     
         3 . The non-volatile memory device of  claim 1 , wherein a cross section of the source/drain regions defines an inverted “U”-shape. 
     
     
         4 . The non-volatile memory device of  claim 1 , wherein the gate structure comprises:
 a control gate line crossing over the active region and extending in a second direction perpendicular to a first direction in which the active region extends; and   a charge storage layer interposed between the active region and the control gate line.   
     
     
         5 . The non-volatile memory device of  claim 4 , further comprising:
 a device isolation layer on the opposing sidewalls of the active region,   wherein the second impurity regions extend towards the substrate beyond a surface of the device isolation layer.   
     
     
         6 . The non-volatile memory device of  claim 5 , wherein the surface of the device isolation layer exposed between the control gate lines is lower than the surface of the active region. 
     
     
         7 . The non-volatile memory device of  claim 5 , wherein the charge storage layer comprises a conductive layer pattern, the conductive layer pattern being arranged with an island shape on the active region. 
     
     
         8 . The non-volatile memory device of  claim 5 , wherein the charge storage layer comprises an insulation layer. 
     
     
         9 . The non-volatile memory device of  claim 1 , wherein the source/drain regions comprise a source region and a drain region on opposite sides of the gate structure, wherein the fin-shaped active region, the gate structure, and the source/drain regions constitute a memory layer, and further comprising:
 a plurality of memory layers stacked on the memory layer, the plurality of memory layers including respective fin-shaped active regions having opposing sidewalls and respective surfaces therebetween, respective gate structures on the respective surfaces thereof, and respective source regions and drain regions in the respective active regions on opposite sides of the respective gate structures.   
     
     
         10 . The non-volatile memory device of  claim 9 , further comprising:
 a contact electrically connecting the drain regions of ones of the plurality of stacked memory layers; and   a common source line electrically connecting the source regions of the ones of the plurality of stacked memory layers.   
     
     
         11 . An electronic device comprising:
 a bus;   a controller electrically connected to the bus;   an input/output device electrically connected to the bus;   an interface electrically connected to the bus; and   a non-volatile memory device electrically connected to the bus, wherein the non-volatile memory device comprises:
 a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate; 
 a gate structure on the surface of the active region; and 
   source/drain regions in the active regions at opposite sides of the gate structure, the source/drain regions respectively comprising a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region, the first impurity region having a doping concentration that is greater than that of the second impurity regions.