Impedance matched lane reversal switching system

Abstract

An impedance matched lane reversal switching system including first and second transceiver pairs, each of the pairs including a transmitter connected to a receiver, the output of the transmitter connected to the input of the receiver and to a node, the node of each pair interconnected with a transmission line and a switching circuit for selectively enabling one of the transmitters of one of the transceiver pairs and disabling the other and selectively utilizing one of the receivers of the other of the transceiver pairs and not the other to selectively reverse an egress side and an ingress side of the lane.

1 . An impedance matched lane reversal switching system comprising:
 first and second transceiver pairs, each of said pairs including a transmitter connected to a receiver, the output of the transmitter connected to the input of the receiver and to a node, the node of each pair interconnected with a transmission line; and   a switching circuit for selectively enabling one of the transmitters of one of said transceiver pairs and disabling the other and selectively utilizing one of the receivers of the other of said transceiver pairs and not the other to selectively reverse an egress side and an ingress side of the lane.   
     
     
         2 . The system of  claim 1  further including a set of terminating resistances interconnected to each said node and to each said transmission line for impedance matching and terminating both the transmitter and receiver of each of said transceiver pairs. 
     
     
         3 . The system of  claim 1  further including a connection to at least two types of devices that have different orientation of their transmitters and receivers. 
     
     
         4 . The system of  claim 3  in which said at least two types of devices include line cards. 
     
     
         5 . The system of  claim 3  in which said at least two types of devices include switch cards. 
     
     
         6 . The system of  claim 1  in which said system is integrated on a single chip. 
     
     
         7 . The system of  claim 6  in which said single chip is disposed on a switch card. 
     
     
         8 . The system of  claim 6  in which said single chip is disposed on a line card. 
     
     
         9 . The system of  claim 1  in which said switching circuit includes a plurality of switching devices for selectively enabling one of said transmitters of one of said transceiver pairs and utilizing one of said receivers of the other said transceiver pairs in response to an external control signal. 
     
     
         10 . The system of  claim 9  in which said switching circuit includes an external control pin. 
     
     
         11 . The system of  claim 1  in which the switching circuit includes a cross bar circuit having at least one input and at least one output for selectively connecting said at least one output to an enabled one of said transmitters of said transceiver pairs and said at least one input to a utilized one of the receivers of the other transceiver pair. 
     
     
         12 . An impedance matched lane reversal switching system comprising:
 first and second transceiver pairs, each of said pairs including a transmitter connected to a receiver, the output of the transmitter connected to the input of the receiver and to a node, the node of each pair interconnected with a transmission line; and   a switching circuit for selectively enabling one of the transmitters of said transceiver pairs and disabling the other in one mode to selectively reverse an egress side and an ingress side of the lane.   
     
     
         13 . A method of impedance matching and lane reversing a switching system comprising the steps of:
 providing first and second transceiver pairs, each of said pairs including a transmitter connected to a receiver, the output of the transmitter connected to the input of the receiver and to a node, the node of each pair interconnected with a transmission line; and   selectively enabling one of the transmitters of one of said transceiver pairs and disabling the other and selectively utilizing one of the receivers of the other of said transceiver pairs and not the other to selectively reverse an egress side and an ingress side of the lane.