Power device packages and methods of fabricating the same

Abstract

Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.

1 - 17 . (canceled) 
     
     
         18 . A method of manufacturing a power device package, the method comprising:
 obtaining a die attach paddle substrate including an interlayer member layer and a conductive pattern formed on the interlayer member layer;   attaching an adhesive layer to a surface of the interlayer member layer opposite to the conductive pattern;   forming a die attach paddle by singulating the die attach paddle substrate and the adhesive layer;   attaching the adhesive layer of the die attach paddle to a top surface of the first power semiconductor chip mounted on the first die attach region on the substrate; and   attaching a lower surface of the second power semiconductor chip to a second die attach region of the die attach paddle.   
     
     
         19 . The method of  claim 18 , wherein the conductive pattern of the die attach paddle substrate comprises a plurality of patterns separated apart from one another. 
     
     
         20 . The method of  claim 18 , wherein the forming of the die attach paddle comprises cutting the interlayer member layer and the adhesive layer between the patterns. 
     
     
         21 . The method of  claim 18 , wherein the die attach paddle substrate comprises a detachable base film detachably attached to the adhesive layer of the die attach paddle substrate. 
     
     
         22 . The method of  claim 21 , wherein forming the die attach paddle further comprises separating the die attach paddle from the base film by using a pick-up method. 
     
     
         23 . The method of  claim 22 , wherein the pick-up method is performed using a die bonder. 
     
     
         24 . The method of  claim 18 , wherein the lower surface of the second power semiconductor chip and the second die attach region of the die attach paddle are attached using a conductive adhesive member. 
     
     
         25 . The method of  claim 18 , further comprising, after the attaching of the lower surface of the second power semiconductor chip, electrically connecting at least one of connection pads of the first power semiconductor chip and connection pads of the second power semiconductor chip and a lead by using a wire.