Input/output circuit

Abstract

In some embodiments, an input/output (I/O) circuit sends and receives a high-level signal and a low-level signal via a coupling capacitance provided on a communication line. The I/O circuit includes a receiving portion including a first detection circuit arranged to detect one of the signals and a second detection circuit arranged to detect the other signal, a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal, and a control circuit configured to control the receiving portion and the transmitting portion. The control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state.

1 . An input/output circuit for sending and receiving a high-level signal and a low-level signal via a coupling capacitance provided on a communication line,
 the input/output circuit comprising:   a receiving portion including a first detection circuit arranged to detect one of the high-level signal and the low-level signal and a second detection circuit arranged to detect the other of the high-level signal and the low-level signal;   a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal; and   a control circuit configured to control the receiving portion and the transmitting portion,   wherein the control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state.   
     
     
         2 . The input/output circuit as recited in  claim 1 , wherein, in the receiving state, when the high-level signal is detected, the control circuit makes the first detection circuit and the second detection circuit turn off and turn on, respectively, and wherein, when the low-level signal is detected, the control circuit makes the first detection circuit and the second detection circuit turn on and turn off, respectively. 
     
     
         3 . The input/output circuit as recited in  claim 1 , wherein, in the receiving state, the control circuit  10  makes the three-value output circuit output the high impedance signal. 
     
     
         4 . The input/output circuit as recited in  claim 1 , wherein, in the transmitting state, when the high-level signal is detected, the control circuit makes the three-value output circuit output a high-level signal, and when the low-level signal is detected, the control circuit makes the three-value output circuit output a low-level signal. 
     
     
         5 . The input/output circuit as recited in  claim 1 , wherein the control circuit includes a register, and the control circuit makes the three-value output circuit active or inactive depending a value of the register. 
     
     
         6 . The input/output circuit as recited in  claim 1 , wherein the first detection circuit is an H-level detector, and the second detection circuit is an L-level detector. 
     
     
         7 . The input/output circuit as recited in  claim 1 , wherein
 the first detection circuit includes a first P-type channel transistor, a first resister, and a first N-type channel transistor connected in series in this order from a power source line between the power source line and a ground,   a gate of the first N-type channel transistor is connected to the communication line,   a first on-off control signal for changing an on-off state of the first P-type channel transistor outputted from the control circuit is inputted to a gate of the first P-type channel transistor, and   a first detection signal is outputted from a connecting portion of the first resister and the first N-type channel transistor to the control circuit,   and wherein   the second detection circuit includes a second P-type channel transistor, a second resister, and a second N-type channel transistor connected in series in this order from the power source line between the power source line and the ground,   a gate of the second P-type channel transistor is connected to the communication line,   a second on-off control signal for changing an on-off state of the second N-type channel transistor outputted from the control circuit is inputted to a gate of the second N-type channel transistor, and   a second detection signal is outputted from a connecting portion of the second P-type channel transistor and the second resister to the control circuit.   
     
     
         8 . The input/output circuit as recited in  claim 1 , wherein the first detection circuit is an H-level detector, and the second detection circuit is an L-level detector. 
     
     
         9 . The input/output circuit as recited in  claim 1 , wherein the input/output circuit is a communication interface circuit arranged between ICs.