Semiconductor integrated circuit

Abstract

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S 2 ) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S 6 ) and a predetermined linearity condition (S 7 ).

1 . A semiconductor integrated circuit comprising:
 a variable delay circuit; and   a test circuit for the variable delay circuit;   wherein the test circuit forms a ring oscillator using the variable delay circuit, causes the ring oscillator to oscillate at the time of test operation and determines whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies predetermined monotonic increase and linearity conditions.   
     
     
         2 . The semiconductor integrated circuit according to  claim 1 , wherein the test circuit stores a first count value of the ring oscillator at a first time and a second count value of the ring oscillator at a second time after a predetermined time elapsed from the first time and determines that the ring oscillator satisfies the monotonic increase condition when the relation of the first count value<the second count value is satisfied. 
     
     
         3 . The semiconductor integrated circuit according to  claim 1 , wherein the test circuit stores a first count value of the ring oscillator at a first time, a second count value of the ring oscillator at a second time after a predetermined time elapsed from the first time and a third count value of the ring oscillator at a third time after a predetermined time elapsed from the second time and determines that the ring oscillator satisfies the linearity condition if a deviation between the third count value and an expected count value at the third time expected from the second count value and the increment of count value of the ring oscillator at the first to the second time falls within a predetermined range. 
     
     
         4 . A semiconductor integrated circuit comprising:
 a first variable delay circuit;   a first switching circuit configured to switch an input to the first variable delay circuit by an external input and an output from the first switching circuit;   a ring oscillator counter configured to count the output of a ring oscillator formed by the first switching circuit selecting the output from the first variable delay circuit and output a count value at a predetermined timing;   a first register configured to store the count value preceding by one count value output by the ring oscillator counter; and   a second register configured to predict an expected count value which the ring oscillator counter is expected to output from the past count value of the ring oscillator counter and store the expected count value;   wherein the count value output by the ring oscillator is compared with the count value stored into the first register and the expected count value stored into the second register to determine whether the first variable delay circuit is normal or abnormal.   
     
     
         5 . The semiconductor integrated circuit according to  claim 4 , wherein if the count value output by the ring oscillator is greater than the count value stored into the first register and a deviation between the count value output by the ring oscillator and the expected count value is equal to or smaller than a predetermined value, it is determined that the first variable delay circuit is normal. 
     
     
         6 . The semiconductor integrated circuit according to  claim 4 , further comprising:
 a second variable delay circuit; and   a second switching circuit configured to switch an input to the second variable delay circuit by an external input and outputs from the first and the second variable delay circuit;   wherein the first switching circuit is configured to enable selecting the output of the second variable delay circuit and the ring oscillator counter counts the output of a ring oscillator including the first and the second variable delay circuit when the first switching circuit selects an output from the second variable delay circuit and the second switching circuit selects an output from the first variable delay circuit.   
     
     
         7 . The semiconductor integrated circuit according to  claim 6 , wherein the delay of the first variable delay circuit and the delay of the second variable delay circuit are complementarily changed to determine whether the variable delay circuit is normal or abnormal. 
     
     
         8 . A semiconductor integrated circuit comprising:
 a first variable delay circuit;   a first delay control circuit including a first digital analog conversion circuit configured to convert a digital signal to the amount of current and controlling the delay of the first variable delay circuit by voltage according to the amount of current; and   a first test circuit for the first delay control circuit;   wherein the first digital analog conversion circuit includes a plurality of unit current sources selected according to the value of a digital signal and the first test circuit determines that the value of a current flowing into each of the plurality of the unit current sources falls within a predetermined range to determine whether the first delay control circuit is normal or abnormal.   
     
     
         9 . The semiconductor integrated circuit according to  claim 8 , further comprising:
 a second variable delay circuit;   a second delay control circuit including a second digital analog conversion circuit configured to convert a digital signal to the amount of current and controlling the delay of the second variable delay circuit by voltage according to the amount of current; and   a second test circuit for the second delay control circuit;   wherein the second digital analog conversion circuit includes a plurality of unit current sources selected according to the value of a digital signal and the second test circuit determines whether the value of a current flowing into each of the plurality of the unit current sources falls within a predetermined range to determine whether the second delay control circuit is normal or abnormal.   
     
     
         10 . The semiconductor integrated circuit according to  claim 9 , wherein the determination results of the first and the second delay control circuit are outputted with the determination results integrated. 
     
     
         11 . The semiconductor integrated circuit according to  claim 9 ,
 wherein the first test circuit includes a current adjustment circuit configured to increase or decrease the amount of current of the second digital analog conversion circuit by a predetermined amount, and   wherein the amount of current flowing into the first digital analog conversion is compared with a first amount of current in which the amount of current flowing into the second digital analog conversion is increased by the current adjustment circuit by a predetermined amount and a second amount of current in which the amount of current flowing into the second digital analog conversion is decreased by the current adjustment circuit by a predetermined amount to determine whether the value of current flowing into the unit current source falls within a predetermined range.   
     
     
         12 . The semiconductor integrated circuit according to  claim 9 ,
 wherein the first test circuit includes a current adjustment circuit configured to increase or decrease the amount of current of the first digital analog conversion circuit by a predetermined amount, and   wherein the amount of current flowing into the second digital analog conversion is compared with a first amount of current in which the amount of current flowing into the first digital analog conversion is increased by the current adjustment circuit by a predetermined amount and a second amount of current in which the amount of current flowing into the first digital analog conversion is decreased by the current adjustment circuit by a predetermined amount to determine whether the value of current flowing into the unit current source falls within a predetermined range.   
     
     
         13 . The semiconductor integrated circuit according to  claim 8 ,
 wherein the first test circuit includes a third digital analog conversion circuit configured to convert a digital signal to the amount of current and a current adjustment circuit configured to increase or decrease the amount of current of the third digital analog conversion circuit by a predetermined amount, and   wherein the amount of current flowing into the first digital analog conversion is compared with a first amount of current in which the amount of current flowing into the third digital analog conversion is increased by the current adjustment circuit by a predetermined amount and a second amount of current in which the amount of current flowing into the second digital analog conversion is decreased by the current adjustment circuit by a predetermined amount to determine whether the value of current flowing into the unit current source falls within a predetermined range.   
     
     
         14 . The semiconductor integrated circuit according to  claim 8 ,
 wherein the first test circuit includes a third digital analog conversion circuit configured to convert a digital signal to the amount of current and a current adjustment circuit configured to increase or decrease the amount of current of the first digital analog conversion circuit by a predetermined amount, and   wherein the amount of current flowing into the third digital analog conversion is compared with a first amount of current in which the amount of current flowing into the first digital analog conversion is increased by the current adjustment circuit by a predetermined amount and a second amount of current in which the amount of current flowing into the first digital analog conversion is decreased by the current adjustment circuit by a predetermined amount to determine whether the value of current flowing into the unit current source falls within a predetermined range.