High coupling memory cell

Abstract

A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

1 . A non-volatile memory device comprising:
 a plurality of first dielectric layers formed over a substrate;   a plurality of isolation trenches formed between each of the first dielectric layers and in the substrate;   a plurality of floating gates, each having multi-level troughs, formed over each of the first dielectric layers and between each pair of isolation trenches;   a second dielectric layer formed over each floating gate; and   a control gate formed over each second dielectric layer.   
     
     
         2 . The non-volatile memory device of  claim 1  wherein the plurality of floating gates and the control gate are doped polysilicon. 
     
     
         3 . The non-volatile memory device of  claim 1  wherein the non-volatile memory device is a flash memory cell. 
     
     
         4 . The non-volatile memory device of  claim 1  wherein the first dielectric layer comprises a tunnel dielectric layer. 
     
     
         5 . The non-volatile memory device of  claim 1  wherein the floating gate comprises a single floating gate layer. 
     
     
         6 . The non-volatile memory device of  claim 1  wherein the second dielectric layer comprises an integrated dielectric layer. 
     
     
         7 . The non-volatile memory device of  claim 1  wherein the plurality of isolation trenches each separate active areas of the device. 
     
     
         8 . The non-volatile memory device of  claim 1  wherein the plurality of isolation trenches each comprise a protruding isolation area that includes an upper portion and a lower portion, wherein the upper portion extends above the first dielectric layer. 
     
     
         9 . The non-volatile memory device of  claim 8  wherein each side of the upper portion has a substantially concave shape. 
     
     
         10 . The non-volatile memory device of  claim 8  wherein the top of the upper portion is below an upper surface of each floating gate. 
     
     
         11 . The non-volatile memory device of  claim 8  wherein the upper portion extends through 50% of the thickness of each floating gate. 
     
     
         12 . The non-volatile memory device of  claim 8  wherein uppermost edges of the upper portion are narrower than edges of the lower portion. 
     
     
         13 . The non-volatile memory device of  claim 1  wherein each trough is 50% of the thickness of each floating gate. 
     
     
         14 . The non-volatile memory device of  claim 1  wherein each trough is formed over an isolation trench. 
     
     
         15 . The non-volatile memory device of  claim 1  wherein each trough is formed adjacent to an isolation trench. 
     
     
         16 . The non-volatile memory device of  claim 1  wherein the second dielectric layer comprises an oxide-nitride-oxide (ONO) layer. 
     
     
         17 . The non-volatile memory device of  claim 1  wherein the second dielectric layer comprises a nitride-oxide (NO) layer.