Driving circuit for power mosfet

Abstract

A driving circuit for a power MOSFET includes a first switch, a second switch, a third switch and a fourth switch. The first switch is connected to a first node, a second node and a first power end. The first power end supplies a first voltage. The second switch is connected to the first node, the second node and a first ground end. The third switch is connected to the second node, a third node and the first power end. The fourth switch is connected to the second node, the third node and a second ground end. The power MOSFET is connected to the third node and a PWM signal is inputted into the first node. The PWM signal has a second voltage lower than the first voltage.

1 . A driving circuit for a power metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:
 a first switch connected to a first node, a second node and a first power end, the first power end supplying a first voltage;   a second switch connected to the first node, the second node and a first ground end;   a third switch connected to the second node, a third node and the first power end; and   a fourth switch connected to the second node, the third node and a second ground end;   wherein the power MOSFET is connected to the third node, a pulse width modulation signal is inputted into the first node, and the pulse width modulation signal has a second voltage lower than the first voltage;   wherein when the pulse width modulation signal is high, the first and fourth switches are turned off and the second and third switches are turned on, so that the first voltage is outputted to the third node through the third switch, so as to turn on the power MOSFET;   when the pulse width modulation signal is low, the first and fourth switches are turned on and the second and third switches are turned off, so that the power MOSFET discharges through the fourth switch and the second ground end.   
     
     
         2 . The driving circuit of  claim 1 , wherein the first switch is a P-type transistor having a gate connected to the first node, a source connected to the second node, and a drain connected to the first power end. 
     
     
         3 . The driving circuit of  claim 1 , wherein the second switch is an N-type transistor having a gate connected to the first node, a drain connected to the second node, and a source connected to the first ground end. 
     
     
         4 . The driving circuit of  claim 1 , wherein the third switch is a P-type transistor having a gate connected to the second node, a source connected to the third node, and a drain connected to the first power end. 
     
     
         5 . The driving circuit of  claim 1 , wherein the fourth switch is an N-type transistor having a gate connected to the second node, a drain connected to the third node, and a source connected to the second ground end. 
     
     
         6 . The driving circuit of  claim 1 , wherein the power MOSFET has a gate connected to the third node, a drain connected to a second power end, and a source connected to a third ground end. 
     
     
         7 . The driving circuit of  claim 1 , wherein when the pulse width modulation signal is high, the first switch is turned off and the second switch is turned on, so that the pulse width modulation signal is converted from high to low at the second node. 
     
     
         8 . The driving circuit of  claim 7 , wherein when the second node is low, the fourth switch is turned off and the third switch is turned on, so that the pulse width modulation signal is converted from low to high at the third node. 
     
     
         9 . The driving circuit of  claim 1 , wherein when the pulse width modulation signal is low, the first switch is turned on and the second switch is turned off, so that the pulse width modulation signal is converted from low to high at the second node. 
     
     
         10 . The driving circuit of  claim 9 , wherein when the second node is high, the fourth switch is turned on and the third switch is turned off, so that the pulse width modulation signal is converted from high to low at the third node.