Display system with frame reuse using divided multi-connector element differential bus connector

Abstract

A method includes reducing power of a first graphics processor by disabling or not using its rendering engine and leaving a display engine of the same first graphics processor capable of outputting display frames from a corresponding first frame buffer to a display. A display frame is rendered by a second graphics processor while the rendering engine of the first graphics processor is in a reduced power state, such as a non-rendering state. The rendered frame is stored in a corresponding second frame buffer of the second graphics processor, such as a local frame buffer and copied from the second frame buffer to the first frame buffer. The copied frame in the first frame buffer is then displayed on a display while the rendering engine of the first graphics processor is in the reduced power state. Accordingly thermal output and power output is reduced with respect to the first graphics processor since it does not do frame generation using its rendering engine, it only uses its display engine to display frames generated by the second graphics processor.

What is claimed is: 
     
         1 . A method comprising:
 reducing power of a rendering engine of a first graphics processor and leaving a display engine of the first graphics processor capable of outputting display frames from a corresponding first frame buffer to a display;   rendering a display frame by a second graphics processor while the rendering engine of the first graphics processor is in a reduced power state;   storing the rendered frame in a corresponding second frame buffer of the second graphics processor;   copying the rendered frame from the second frame buffer to the first frame buffer; and   displaying the copied frame in the first frame buffer on a display while the rendering engine of a first graphics processor is in the reduced power state.   
     
     
         2 . The method of  claim 1  wherein copying the rendered frame from the second frame buffer to the first frame buffer comprises communicating the rendered frame to the first frame buffer via a differential communication bus. 
     
     
         3 . The method of  claim 1  wherein the reduced power state of the rendering engine of the first graphics processor is a low power state such that the rendering engine is unable to render a display frame. 
     
     
         4 . A system comprising:
 a first device comprising:
 a first graphics processor that comprises at least a rendering engine and a display engine; and 
 a corresponding first frame buffer, operatively coupled to the first graphics processor, operative to store rendered frames generated by the rendering engine, 
 the first device also being operative to reduce power of the rendering engine of the first graphics processor and leave the display engine of the first graphics processor capable of outputting display frames from the corresponding first frame buffer; and 
 a second device, in communication with the first device and comprising:
 a second graphics processor and corresponding second frame buffer, the second graphics processor operative to render a display frame while the rendering engine of the first graphics processor is in a reduced power state and store the rendered frame in the corresponding second frame buffer of the second graphics processor, 
 the second device operative to copy the rendered frame from the second frame buffer to the first frame buffer of the second device; and 
 the display engine in the first graphics processor of the first device operative to display the copied frame in the first frame buffer on a display while the rendering engine of a first graphics processor is in the reduced power state. 
 
   
     
     
         5 . The system of  claim 4  wherein the first and second graphics processors are linked by a differential communication bus and wherein copying the rendered frame from the second frame buffer to the first frame buffer comprises communicating the rendered frame to the first frame buffer via the differential communication bus and wherein rendering commands are received by the second device from the first device via the differential communication bus. 
     
     
         6 . An apparatus comprising:
 a graphics processor and corresponding frame buffer, the graphics processor operative to render a display frame in response to a rendering engine of another graphics processor being in a reduced power state and operative to store the rendered frame in the corresponding frame buffer,   logic operative to cause copying of the rendered frame from the corresponding frame buffer to a frame buffer of another graphics processor in response to the rendering engine of the other graphics processor being in a reduced power state; and   the display engine in the first graphics processor of the first device operative to display the copied frame in the first frame buffer on a display while the rendering engine of a first graphics processor is in the reduced power state.   
     
     
         7 . The apparatus of  claim 6  wherein the logic is incorporated in the graphics processor and wherein the first and second graphics processors perform a handshaking operation to indicate when the first graphics processor is ready to receive a next frame from the second graphics processor. 
     
     
         8 . The apparatus of  claim 6  wherein the logic is incorporated in the graphics processor and wherein the first graphics processor reads a next frame from the second frame buffer of the second graphics processor.