Interposer and method for manufacturing the same

Abstract

An interposer includes: an insulation plate where a via is formed, the insulation plate including a resin or a ceramic; a first upper redistribution layer electrically connected to the via along a circuit pattern designed on the top surface of the insulation plate; a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer; a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern designed; a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer.

1 . An interposer comprising:
 an insulation plate where a via is formed, the insulation plate including a resin or a ceramic;   a first upper redistribution layer formed on the top surface of the insulation plate to be electrically connected to the via along a designed circuit pattern;   a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer;   a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern;   a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and   an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer.   
     
     
         2 . The interposer of  claim 1 , further comprising:
 a lower redistribution layer formed on the bottom surface of the insulation plate to be electrically connected to the via along a designed circuit pattern;   a lower protection layer laminated to expose a portion of the lower redistribution layer and protecting the lower redistribution layer; and   an under bump metallization (UBM) formed at the exposed portion of the lower redistribution layer.   
     
     
         3 . A method for manufacturing an interposer, the method comprising:
 forming a via hole in an insulation plate including a resin or a ceramic;   simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate;   plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and   forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer.   
     
     
         4 . The method of  claim 3 , further comprising forming an under bump metallization (UBM) on the first upper redistribution layer and the lower redistribution layer exposed after the formation of the first upper protection layer and the lower protection layer. 
     
     
         5 . The method of  claim 3 , further comprising:
 forming a second upper redistribution layer on the top surface of the insulation plate along a designed circuit pattern; and   forming a second upper protection layer to expose a portion of the second upper redistribution layer.   
     
     
         6 . The method of  claim 5 , further comprising forming an under bump metallization (UBM) on the second upper redistribution layer exposed after the formation of the second upper protection layer. 
     
     
         7 . The method of  claim 5 , wherein the second upper redistribution layer and the second upper protection layer are formed using a semiconductor manufacturing process in order for implementation of fine pitches. 
     
     
         8 . The method of  claim 3 , wherein the forming of the via hole on the insulation plate comprises forming a seed layer in a region where the resin or ceramic inside the insulation plate is exposed. 
     
     
         9 . The method of  claim 3 , wherein the plating of the copper and the forming of the first upper redistribution layer and the lower redistribution layer comprise plating the copper on both sides of the insulation plate and the via hole, and removing the resists. 
     
     
         10 . The method of  claim 3 , wherein the insulation plate is a copper clad laminate (CCL).