Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device

Abstract

A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.

1 - 6 . (canceled) 
     
     
         7 . A computer-implemented pattern design method of designing a pattern of a semiconductor circuit to be formed on a substrate, comprising:
 creating, by a computer, a design pattern by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells;   analyzing, by the computer, an electrical characteristic of the semiconductor circuit corresponding to the design pattern;   cutting, by the computer, a part of the design pattern on the basis of an analysis result of the electrical characteristic;   predicting, by the computer, a predictive pattern to be formed on the substrate by the cut part of the design pattern;   checking, by the computer, a difference amount between the predictive pattern and a target pattern to be formed on the substrate;   comparing, by the computer, the difference amount with a predetermined allowable variation amount;   outputting, by the computer, error data if the difference amount is larger than the allowable variation amount in the comparing;   extracting, by the computer, hot spot information on the basis of the error data; and   correcting, by the computer, at least one of the placement and the routing of the part of the design pattern corresponding to the predictive pattern in accordance with the hot spot information.   
     
     
         8 . The method according to  claim 7 , further comprising:
 creating, by the computer, mask pattern data based on the design pattern after correcting at least one of the placement and routing;   predicting, by the computer, a predictive pattern to be formed on the substrate by the mask pattern data;   checking, by the computer, a difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data;   comparing, by the computer, the difference amount with a predetermined allowable variation amount; and   correcting, by the computer, at least one of the placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern if the difference amount is larger than the allowable variation amount in the comparison.   
     
     
         9 . The method according to  claim 7 , wherein creating the mask pattern data comprises executing a correlation test between the mask pattern data and a circuit diagram of the semiconductor circuit and a design rule violation test of the mask pattern data. 
     
     
         10 . The method according to  claim 7 , further comprising executing, by the computer, optical proximity correction for the mask pattern data after creating the mask pattern data. 
     
     
         11 . The method according to  claim 7 , wherein the cut part of the design pattern includes a design pattern corresponding to a critical path portion in the semiconductor circuit. 
     
     
         12 . The method according to  claim 7 , wherein the cut part of the design pattern includes a design pattern corresponding to a portion except a critical path portion in the semiconductor circuit. 
     
     
         13 . A computer-implemented pattern design method of designing a pattern of a semiconductor circuit to be formed on a substrate, comprising:
 creating, by a computer, a design pattern by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells;   analyzing, by the computer, an electrical characteristic of the plurality of cells corresponding to the design pattern;   determining, by the computer, whether an analysis result of the electrical characteristic falls within a predetermined range;   executing, by the computer, one of replacement of the cells and correction of the routing if the analysis result of the electrical characteristic of the cells falls outside the predetermined range in the determination;   predicting, by the computer, a predictive pattern to be formed on the substrate by a part of the design pattern corresponding to the cells if the analysis result of the electrical characteristic of the cells falls within the predetermined range in the determining;   checking, by the computer, a difference amount between the predictive pattern and a target pattern to be formed on the substrate;   comparing, by the computer, the difference amount with a predetermined allowable variation amount;   outputting, by the computer, error data if the difference amount is larger than the allowable variation amount in the comparing;   extracting, by the computer, hot spot information on the basis of the error data; and   correcting, by the computer, at least one of the placement and the routing of the part of the design pattern corresponding to the predictive pattern in accordance with the hot spot information.   
     
     
         14 . The method according to  claim 13 , further comprising:
 creating, by the computer, mask pattern data based on the design pattern after correcting at least one of the placement and routing;   predicting, by the computer, a predictive pattern to be formed on the substrate by the mask pattern data;   checking, by the computer, a difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data;   comparing, by the computer, the difference amount with a predetermined allowable variation amount; and   correcting, by the computer, at least one of the placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern if the difference amount is larger than the allowable variation amount in the comparison.   
     
     
         15 . The method according to  claim 13 , wherein creating the mask pattern data comprises executing a correlation test between the mask pattern data and a circuit diagram of the semiconductor circuit and a design rule violation test of the mask pattern data. 
     
     
         16 . The method according to  claim 13 , further comprising executing, by the computer, optical proximity correction for the mask pattern data after creating the mask pattern data. 
     
     
         17 . The method according to  claim 13 , wherein in replacement of the cell, a cell for which the analysis result of the electrical characteristic falls within the predetermined range is selected from a library registering a plurality of cells for replacement and replaces the cell. 
     
     
         18 . The method according to  claim 17 , wherein the library registers a first cell group, a second cell group, and a third cell group, the first cell group including typical cells having a transistor and a line width created by a standard design rule, the second cell group including cells having a transistor and a line width created by a design rule thicker than the standard design rule, and the third cell group including cells having a transistor and a line width created by a design rule thinner than the standard design rule. 
     
     
         19 . A computer program product tangibly embodied in a storage device containing instructions which cause a computer to perform a method for designing a pattern of a semiconductor circuit to be formed on a substrate, the method comprising:
 creating a design pattern by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells;   analyzing an electrical characteristic of the semiconductor circuit corresponding to the design pattern;   determining whether an analysis result of the electrical characteristic satisfies a predetermined allowance of the electrical characteristic;   creating mask pattern data based on the design pattern when the analysis result of the electrical characteristic satisfies the allowance;   creating the design pattern again when the analysis result of the electrical characteristic does not satisfy the allowance;   predicting a predictive pattern to be formed on the substrate by the mask pattern data;   checking a difference amount between the predictive pattern and a target pattern to be formed on the substrate;   comparing the difference amount with a predetermined allowable variation amount; and   correcting at least one of the placement of the cells and the routing among the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern if the difference amount is larger than the allowable variation amount in the comparison.   
     
     
         20 . A method of manufacturing a semiconductor device by forming a pattern of a semiconductor circuit on a substrate by using a photomask, comprising forming the photomask, the photomask being formed by:
 creating a design pattern by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells;   analyzing an electrical characteristic of the semiconductor circuit corresponding to the design pattern;   determining whether an analysis result of the electrical characteristic satisfies a predetermined allowance of the electrical characteristic;   creating mask pattern data based on the design pattern when the analysis result of the electrical characteristic satisfies the allowance;   creating the design pattern again when the analysis result of the electrical characteristic does not satisfy the allowance;   predicting a predictive pattern to be formed on the semiconductor substrate by the mask pattern data;   checking a difference amount between the predictive pattern and a target pattern to be formed on the semiconductor substrate;   comparing the difference amount with a predetermined allowable variation amount; and   correcting at least one of the placement of the cells and the routing among the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern if the difference amount is larger than the allowable variation amount in the comparing.   
     
     
         21 . (canceled)