Semiconductor devices including lower and upper device isolation patterns

Abstract

In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.

1 . A semiconductor device comprising:
 a semiconductor substrate including trenches defining active regions;   lower and upper device isolation patterns disposed in the trenches;   an intergate insulation pattern and a control gate electrode disposed on the semiconductor substrate to cross over the active regions;   a charge storage electrode between the control gate electrode and the active regions; and   a gate insulation pattern between the charge storage electrode and the active regions,   wherein the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.   
     
     
         2 . The device of  claim 1 , wherein the lower device isolation pattern is a chemically vapor deposited silicon oxide film and the upper device isolation pattern is a high-density plasma silicon oxide film. 
     
     
         3 . The device of  claim 1 , wherein the lower device isolation pattern includes a discontinuous interface extending toward a surface of the semiconductor substrate from a surface of the lower device isolation pattern, and wherein the upper device isolation pattern covers the discontinuous interface. 
     
     
         4 . The device of  claim 1 , further comprising spacers disposed at sidewalls of the charge storage electrode under the intergate insulation pattern,
 wherein the spacers expose a top surface of the upper device isolation pattern.   
     
     
         5 . The device of  claim 4 , wherein the upper device isolation pattern comprises a recess region between the spacers, and wherein a bottom surface of the recess region is lower than a bottom surface of the spacers and higher than a top surface of the lower device isolation pattern. 
     
     
         6 . The device of  claim 1 , wherein an upper surface of the lower device isolation pattern is substantially planar. 
     
     
         7 . The device of  claim 3 , wherein the upper device isolation pattern is free of discontinuous interfaces. 
     
     
         8 . A semiconductor device comprising:
 a semiconductor substrate including trenches defining active regions;   lower and upper device isolation patterns disposed in the trenches;   an intergate insulation pattern and a control gate electrode disposed on the semiconductor substrate to cross over the active regions;   a charge storage electrode between the control gate electrode and the active regions; and   a gate insulation pattern between the charge storage electrode and the active regions,   wherein the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions,   wherein the lower device isolation pattern includes a discontinuous interface extending toward a surface of the semiconductor substrate from a surface of the lower device isolation pattern, and   wherein the upper device isolation pattern covers the discontinuous interface.   
     
     
         9 . A semiconductor device comprising:
 a semiconductor substrate including trenches defining active regions;   lower and upper device isolation patterns disposed in the trenches;   an intergate insulation pattern and a control gate electrode disposed on the semiconductor substrate to cross over the active regions;   a charge storage electrode between the control gate electrode and the active regions; and   a gate insulation pattern between the charge storage electrode and the active regions,   wherein the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions,   wherein the lower device isolation pattern includes a discontinuous interface extending toward a surface of the semiconductor substrate from a surface of the lower device isolation pattern,   wherein the upper device isolation pattern covers the discontinuous interface, and   wherein the upper device isolation pattern is free of discontinuous interfaces.