Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device

Abstract

A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.

1 . A process, comprising:
 forming a first semiconductor layer of a first type of conductivity and of a first resistivity value on a semiconductor substrate of the first type of conductivity;   forming a second semiconductor layer of a second type of conductivity and of a second resistivity value on said first semiconductor layer;   forming, in said second semiconductor layer, a plurality of sets of implanted regions of the first type of conductivity, the sets of implanted regions being spaced apart from each other in a first direction, each set including plural implanted regions aligned with and spaced apart from each other in a second direction transverse to the first direction;   forming, above said second semiconductor layer, a surface semiconductor layer of the first type of conductivity and of a third resistivity value;   forming in said surface semiconductor layer body regions of the second type of conductivity, said body regions being aligned with portions of said second semiconductor layer between said sets of implanted regions; and   forming, from the sets of implanted regions, a plurality of electrically continuous implanted column regions along said second semiconductor layer by carrying out a thermal diffusion step, said plurality of electrically continuous implanted column regions delimiting a plurality of column regions of the second type of conductivity aligned with said body regions.   
     
     
         2 . A process according to  claim 1 , wherein:
 forming the second semiconductor layer includes forming a plurality of semiconductor layers of the second type of conductivity on said first semiconductor layer; and   forming the plurality of sets of implanted regions includes forming, in each layer of the plurality of semiconductor layers a respective plurality of implanted regions of the first type of conductivity using respective selective implant steps with a respective implant doses, wherein for each layer of the plurality of semiconductor layers, said implanted regions are spaced apart from each other in the first direction, said respective plurality of implanted regions forming, during said thermal diffusion step, said plurality of electrically continuous implanted column regions.   
     
     
         3 . A process according to  claim 2  wherein said plurality of semiconductor layers have all a same resistivity value. 
     
     
         4 . A process according to  claim 1  wherein forming said plurality of sets of implanted regions includes using an implant dose that balances a dopant concentration of the second semiconductor layer. 
     
     
         5 . A process according to  claim 1  wherein said first resistivity value is equal to said third resistivity value. 
     
     
         6 . A process according to  claim 1  wherein said semiconductor layers are grown epitaxially. 
     
     
         7 . A process according to  claim 6  wherein said surface semiconductor layer is obtained by dopant implantation of the first type of conductivity in a layer grown epitaxially of the second type of conductivity. 
     
     
         8 . A process according to  claim 1  wherein said semiconductor layers of the second type of conductivity are made of layers each having a thickness comprised between 2 and 10 μm. 
     
     
         9 . A process according to  claim 1  wherein said second semiconductor layer has a lower thickness than said first semiconductor layer. 
     
     
         10 . A process according to  claim 1  wherein said first semiconductor layer of the first type of conductivity is made of layer having a thickness comprised between 2 and 20 μm. 
     
     
         11 . A process according to  claim 9  wherein the first resistivity value of said first semiconductor layer is comprised between 0.5 and 5 ohm*cm. 
     
     
         12 . A process according to  claim 1  wherein said thermal diffusion step is carried out with a temperature greater than 1150° C., for four hours with a oxygen environment. 
     
     
         13 . A process according to  claim 1  wherein each region said plurality of column regions has a maximum width less than a maximum width of each region of said plurality of electrically continuous implanted column regions. 
     
     
         14 . A process according to  claim 1 , wherein forming the plurality of electrically continuous implanted column regions includes obtaining a flat dopant concentration within each implanted column region by carrying out said thermal diffusion step with a temperature greater than 1150° C., and each region of said plurality of column regions has a maximum width less than a maximum width of each region of said plurality of electrically continuous implanted column regions. 
     
     
         15 . A process according to  claim 1 , wherein dopant concentrations of said plurality of electrically continuous implanted column regions are less then dopant concentrations of said plurality of column regions. 
     
     
         16 . A process, comprising:
 forming a drain semiconductor layer on a semiconductor substrate of a first type of conductivity, the drain semiconductor layer including a first semiconductor layer on said semiconductor substrate, a second semiconductor layer above the first semiconductor layer, and a semiconductor surface layer above the second semiconductor layer, the first semiconductor layer and surface layer each having the first type of conductivity and the second semiconductor layer having a second type of conductivity;   forming a plurality of body regions of the second type of conductivity in said semiconductor surface layer;   forming a first plurality of column regions of the first type of conductivity in said drain semiconductor layer; and   forming a second plurality of column regions of the second type of conductivity in said drain semiconductor layer, each of the column regions of the first plurality being laterally delimited by consecutive column regions of the second plurality, each of the column regions of the second plurality being laterally delimited by consecutive column regions of the first plurality, said second plurality of column regions being vertically aligned with said plurality of body regions, respectively, and each column region of said first plurality of column regions including a plurality of doped regions of the first type of conductivity positioned in contact with, and on top of, one another in the second semiconductor layer.   
     
     
         17 . A process according to  claim 16 , wherein forming the drain semiconductor layer includes:
 forming the second semiconductor layer by forming a plurality of semiconductor layers of the second type of conductivity on said first semiconductor layer; and   forming the first plurality of column regions includes forming, in each layer of the plurality of semiconductor layers a respective set of the doped regions of the first type of conductivity, wherein for each layer of the plurality of semiconductor layers, said doped regions are laterally spaced apart from each other.   
     
     
         18 . A process according to  claim 16 , wherein each region of said second plurality of column regions has a maximum width less than a maximum width of each region of said first plurality of column regions. 
     
     
         19 . A process according to  claim 16 , wherein forming the first plurality of column regions includes obtaining a flat dopant concentration within each implanted column region by carrying out a thermal diffusion step. 
     
     
         20 . A process according to  claim 16 , wherein the first semiconductor layer and the surface layer are epitaxial layers of the first type of conductivity and the second semiconductor layer is an epitaxial layer of the second type of conductivity. 
     
     
         21 . A process of making a multi-drain power electronic device, comprising:
 forming a drain semiconductor layer on a semiconductor substrate of a first type of conductivity, the drain semiconductor layer including a first semiconductor layer on said semiconductor substrate, a second semiconductor layer above the first semiconductor layer, and a semiconductor surface layer above the second semiconductor layer, the first semiconductor layer being of said first type of conductivity and the second semiconductor layer having a second type of conductivity;   forming a plurality of body regions of the second type of conductivity in said semiconductor surface layer; and   forming a first plurality of column regions of the first type of conductivity in said drain semiconductor layer and delimiting a second plurality of column regions of the second type of conductivity, each region of said second plurality of column regions being aligned with one of said plurality of body regions, each column region of said first plurality of column regions including a plurality of doped regions of the first type of conductivity positioned in contact with, and on top of, one another in the second semiconductor layer, and each of said first and second pluralities of column regions having a substantially flat concentration profile.   
     
     
         22 . A process according to  claim 21 , wherein forming the drain semiconductor layer includes:
 forming the second semiconductor layer by forming a plurality of semiconductor layers of the second type of conductivity on said first semiconductor layer; and   forming the first plurality of column regions includes forming, in each layer of the plurality of semiconductor layers a respective set of the doped regions of the first type of conductivity, wherein for each layer of the plurality of semiconductor layers, said doped regions are laterally spaced apart from each other.   
     
     
         23 . A process according to  claim 21 , wherein each region of said second plurality of column regions has a maximum width less than a maximum width of each region of said first plurality of column regions. 
     
     
         24 . A process according to  claim 21 , wherein forming the first plurality of column regions includes obtaining the substantially flat concentration profile within each column region of the first plurality by carrying out a thermal diffusion step with a temperature greater than 1150° C. 
     
     
         25 . A process according to  claim 21 , wherein the first semiconductor layer and the surface layer are epitaxial layers of the first type of conductivity and the second semiconductor layer is an epitaxial layer of the second type of conductivity.