Semiconductor device having multi-gate structure and method of manufacturing the same

Abstract

Provided are a semiconductor device having a mesa-type active region including a plurality of slabs and a method of manufacturing the semiconductor device. The semiconductor device includes a first active region and a second active region. The first active region is formed in a line-and-space pattern on a substrate and includes the slabs, each slab having a first surface, a second surface facing a direction opposite to the first side, and a top surface. The first active region and the second active region are composed of identical or different materials. The second active region contacts at least one end of each of the slabs on the substrate to connect the slabs to one another The method includes forming a first active region in a line-and-space pattern on the substrate and forming the second active region.

1 . A method of manufacturing a semiconductor, the method comprising:
 forming a first active region on a substrate, the first active region being composed of a first material;   forming a second active region on the substrate, the second active region contacting at least a portion of the first active region and being composed of a second material;   forming a gate dielectric layer on the first active region; and   forming a gate on the gate dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein the first active region is formed in a line-and-space pattern. 
     
     
         3 . The method of  claim 1 , wherein the first material and the second material are different from each other. 
     
     
         4 . The method of  claim 1 , wherein the forming the first active region comprises forming a plurality of slabs extending on the substrate in a first direction, each slab having a first surface, a second surface facing a direction opposite to the first side, and a top surface. 
     
     
         5 . The method of  claim 4 , wherein the top surface of each of the slabs is disposed a first distance above the substrate, and a top surface of the second active region is disposed a second distance above the substrate, the second distance being equal to or greater than the first distance. 
     
     
         6 . The method of  claim 4 , wherein the second active region contacts both ends of the slabs and extends in a second direction orthogonal to the first direction. 
     
     
         7 . The method of  claim 4 , wherein the second active region has an overlap region that contacts a portion of the first surface, the second surface and the top surface of each of the slabs. 
     
     
         8 . The method of  claim 4 , wherein the forming the second active region comprises:
 forming a mask pattern covering a portion of each of the slabs on the substrate such that both of the ends of each of the slabs are exposed;   forming a second material layer covering both of the exposed ends of each of the slabs and the mask pattern by depositing the second material; and   forming the second active region by planarizing the second material layer.   
     
     
         9 . The method of  claim 8 , wherein the mask pattern is an SiON layer, an Si 3 N 4  layer, or an SiO 2  layer, or a combination of the same. 
     
     
         10 . The method of  claim 9 , wherein the mask pattern includes an SiON layer and an Si 3 N 4  layer stacked sequentially. 
     
     
         11 . The method of  claim 8 , wherein the mask pattern covers only a portion of the top surface of each of the slabs such that the top surface of each of the slabs can be partially exposed around the mask pattern after the mask pattern is formed. 
     
     
         12 . The method of  claim 8 , wherein the second material layer is planarized using the mask pattern as an etch-stop layer. 
     
     
         13 . The method of  claim 12 , wherein the mask pattern comprises an SiON layer contacting each of the slabs and an Si 3 N 4  layer forming a top surface of the mask pattern. 
     
     
         14 . The method of  claim 8 , wherein the second material layer is planarized by chemical mechanical polishing or back etching. 
     
     
         15 . The method of  claim 1 , wherein the first material is monocrystalline silicon, and the second material is polysilicon, amorphous silicon, or a semi-conductor compound containing silicon. 
     
     
         16 . The method of  claim 1 , wherein the gate dielectric layer contains SiO 2 , SiON, Si 3 N 4 , Ge x O y N z , Ge x Si y O z , HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , or Ta 2 O 5 . 
     
     
         17 . The method of  claim 4 , wherein the foaming the gate includes forming a gate line extending in a second direction orthogonal to the first direction such that the gate line covers the first surface, the second surface and the top surface of each of the slabs to form the gate. 
     
     
         18 . The method of  claim 17 , wherein the gate line is composed of conductive polysilicon, metal, metallic nitride, or metal silicide. 
     
     
         19 . The method of  claim 1 , further comprising preparing a silicon-on-insulator substrate as the substrate, the silicon-on-insulator substrate comprising a buried oxide layer and a monocrystalline silicon layer formed on the buried oxide layer, and the first active region is formed by patterning the monocrystalline silicon layer.