Semiconductor devices including first and second bit lines

Abstract

In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line.

1 . A semiconductor device comprising:
 a plurality of first bit lines and a plurality of first contacts connected to respective ones of the first bit lines;   a plurality of spacers on sidewalls of the first bit lines; and   a second bit line self-alignedly disposed between adjacent ones of the spacers, and a second contact self-aligned with and connected to the second bit line.   
     
     
         2 . The semiconductor device of  claim 1 , wherein an overlapping area between one of the first bit lines and the one of the first contacts connected thereto is larger than an overlapping area between the second bit line and the second contact. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a height of one of the first bit lines is different from a height of the second bit line. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a width of one of the first bit lines is different from a width of the second bit line. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a string select line, a ground select line, and a plurality of word lines between the string select line and the ground select line, the first contacts and the second contact being electrically connected to respective drain regions outside the string select line. 
     
     
         6 . The semiconductor device of  claim 5 , wherein a distance between the string select line and one of the first contacts is different from a distance between the string select line and the second contact. 
     
     
         7 . A non-volatile memory device comprising:
 a substrate including a plurality of active regions defined by a device isolation region;   a string select line, a ground select line, and a plurality of word lines disposed between the string select line and the ground select line, the string and ground select lines and the plurality of word lines crossing over the active regions;   an insulation layer covering the string select line, the ground select line, the plurality of word lines, and the active regions;   first contacts through the insulation layer and electrically connected to odd-numbered ones of the active regions;   first bit lines electrically connected to respective first contacts;   a plurality of spacers on sidewalls of the first bit lines; and   a second bit line self-alignedly disposed between adjacent ones of the spacers, and a second contact self-aligned with and connected to the second bit line.   
     
     
         8 . The non-volatile memory device of  claim 7 , wherein an overlapping area between one of the first contacts and the one of the first bit lines connected thereto is larger than an overlapping area between the second contact and the second bit line. 
     
     
         9 . The non-volatile memory device of  claim 7 , wherein a distance between the string select line and one of the first contacts is different from a distance between the string select line and the second contact. 
     
     
         10 . The non-volatile memory device of  claim 7 , wherein a height of one of the first bit lines is different from a height of the second bit line. 
     
     
         11 . The non-volatile memory device of  claim 7 , wherein a width of one of the first bit lines is different from a width of the second bit line.