Gated Diode Memory Cells

Abstract

A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

1 . A memory array comprising a plurality of gated diode memory cells, each of the plurality of gated diode memory cells comprising:
 at least one transistor; and   a gated diode in signal communication with the at least one transistor.   
     
     
         2 . A memory array as defined in  claim 1 , the array comprising a plurality of rows and a plurality of columns of gated diode memory cells. 
     
     
         3 . A memory array as defined in  claim 1  wherein the plurality of gated diode memory cells comprises 2T1D memory cells arranged in rows, each 2T1D memory cell of at least part of a row sharing a common Read Device GND. 
     
     
         4 . A memory array as defined in  claim 1  wherein the source terminal of the at least one transistor can be biased at a voltage. 
     
     
         5 . A memory array as defined in  claim 3  wherein each 2T1D memory cell of at least part of a row shares a common biasing voltage line.