Metallurgy for copper plated wafers

Abstract

Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer. An electrically insulating protective layer overlies the first aluminum metallization layer and the top wafer fabrication passivation layer. The protective layer is preferably formed from an organic material and includes a plurality of contact openings. Underbump metallization stacks are formed in the contact openings. Each underbump metallization stack is electrically connected to the first aluminum metallization layer through its associated contact opening in the protective layer. Solder bumps are preferably then adhered to the underbump metallization stacks.

1 . An integrated circuit wafer comprising a multiplicity of dice, the dice each including a multiplicity of integrated circuits and a plurality of contact pads that are exposed through contact pad openings formed in a top wafer fabrication passivation layer, the wafer further including:
 a patterned copper layer formed over the top wafer fabrication passivation layer, wherein the patterned copper layer is electrically coupled to at least some of the contact pads through the contact pad openings;   a titanium metallization layer positioned between the contact pads and the patterned copper layer that acts as an electrically conductive barrier layer between the contact pads and the patterned copper layer;   an electrically insulating protective layer that overlies the patterned copper layer and the top wafer fabrication passivation layer, there being a plurality of contact openings in the protective layer; and   a plurality of underbump metallization stacks, each underbump metallization stack being electrically connected to the patterned copper layer through an associated contact opening in the protective layer, wherein peripheral portions of the underbump metallization stacks extend over at least some adjacent portions of the protective layer; and   wherein the underbump metallization stacks each include, a titanium layer in contact with the patterned copper layer, an aluminum layer in contact with the titanium layer, a nickel vanadium layer that overlies the aluminum layer; and a second copper layer that overlies the nickel vanadium layer.   
     
     
         2 . A wafer as recited in  claim 1 , wherein each die further comprises at least one trim pad that is exposed through a trim pad opening formed in the top wafer fabrication passivation layer, and wherein:
 a segment the patterned copper layer is electrically coupled to each trim pad;   trim openings are also formed in the protective layer;   a trim pad metallization stack is formed in each trim opening;   the uppermost exposed layer of the trim pad metallization stack is formed from a non-solder wettable material; and   the uppermost exposed layer of the underbump metallization stack is formed from a solder wettable material.   
     
     
         3 . A method of processing an integrated circuit wafer that includes a multiplicity of dice, the dice each including a plurality of contact pads that are exposed through contact pad openings formed in a top wafer fabrication passivation layer, the method including:
 sputtering a titanium metallization layer over the contact pads and the wafer fabrication passivation layer;   sputtering a copper seed layer over the titanium metallization layer;   plating copper on portions of the copper seed layer to thicken desired portions of the copper seed layer into a patterned routing layer, wherein the patterned routing layer is electrically coupled to at least some of the contact pads through the contact pad openings;   removing excess portions of the titanium metallization layer and the copper seed layer;   forming an organic, electrically insulating protective layer over the patterned routing layer and the top wafer fabrication passivation layer, and forming a plurality of contact openings in the protective layer; and   forming a plurality of underbump metallization stacks in the contact openings, each underbump metallization stack being electrically connected to the patterned copper layer through an associated contact opening in the protective layer, wherein peripheral portions of the underbump metallization stacks extend over at least some adjacent portions of the protective layer.   
     
     
         4 . A method as recited in  claim 3 , further comprising:
 forming a second titanium metallization layer over the patterned routing layer and under the protective layer; and   forming a first aluminum metallization layer over the second titanium metallization layer and under the protective layer; and   wherein the underbump metallization stacks are formed to include a second aluminum layer in contact with the first aluminum layer.   
     
     
         5 . A method as recited in  claim 4 , wherein the underbump metallization stacks are further formed to include a nickel vanadium layer that overlies the second aluminum layer and a copper layer that overlies the nickel vanadium layer. 
     
     
         6 . A method as recited in  claim 3 , wherein the underbump metallization stacks are formed to include a second titanium layer that overlies the routing layer, an aluminum layer that overlies the second titanium layer, a nickel vanadium layer that overlies the second aluminum layer and a copper layer that overlies the nickel vanadium layer. 
     
     
         7 . A method as recited in  claim 3 , wherein the wafer further comprises trim pads and wherein the trim pads are part of the copper routing layer and wherein the organic protective layer is arranged to overlie the trim pads. 
     
     
         8 . A method as recited in  claim 3 , wherein the wafer further comprises trim pads and wherein the trim pads are part of the copper routing layer and wherein the organic protective layer has trim pad openings that overlie the trim pads, and wherein trim pad metallization stacks are formed in the trim pad openings, each trim pad metallization stack being electrically connected to the patterned copper layer through an associated trim pad opening in the protective layer, and wherein at least some peripheral portions of the trim pad metallization stacks extend over at least some adjacent portions of the protective layer.