Push-pull fpga cell

Abstract

A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.

1 . A flash memory cell including:
 a p-channel flash transistor having a source, a drain, a floating gate, and a control gate;   an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate;   a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain; and   an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.