TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices

Abstract

A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

1 . An integrated circuit (IC), comprising:
 a substrate having a substrate thickness comprising a top semiconductor surface and a bottom surface opposite said top semiconductor surface;
 at least one TSV including a dielectric liner and an electrically conductive filler material on said dielectric liner, said TSV extending from said top semiconductor surface to a protruding integral TSV tip that protrudes out from said bottom surface of said substrate; 
 wherein said protruding integral TSV tip comprises said electrically conductive filler material and has a tip height that is 1 to 50 μm, and a dielectric tip liner comprising said dielectric liner, wherein a height of said dielectric tip liner is 10 to 90% of said tip height to provide an exposed tip portion on a distal end of said protruding integral TSV tip. 
   
     
     
         2 . The IC of  claim 1 , wherein said tip height is 10 to 40 μm. 
     
     
         3 . The IC of  claim 1 , wherein said electrically conductive filler material comprises copper or tungsten and said dielectric liner comprises silicon oxide, silicon nitride, silicon oxynitride or a polyimide. 
     
     
         4 . The IC of  claim 1 , wherein said electrically conductive filler material comprises at least one metal, wherein a concentration of said metal on said bottom surface of said substrate is <1×10 12  atoms/cm 2 . 
     
     
         5 . The IC of  claim 1 , wherein substrate comprises a bulk silicon comprising substrate, said electrically conductive filler material comprises copper or tungsten, and said dielectric liner comprises silicon oxide, silicon nitride, silicon oxynitride or a polyimide. 
     
     
         6 . An electronic assembly, comprising:
 an integrated circuit (IC) die, comprising:
 a substrate having a substrate thickness comprising a top semiconductor surface and a bottom surface opposite said top semiconductor surface; 
 at least one TSV including a dielectric liner and an electrically conductive filler material on said dielectric liner, said TSV extending from said top semiconductor surface to a protruding integral TSV tip that protrudes out from said bottom surface of said substrate; 
 wherein said protruding integral TSV tip comprises said electrically conductive filler material and has a tip height that is 1 to 50 μm, and a dielectric tip liner comprising said dielectric liner, wherein a height of said dielectric tip liner is 10 to 90% of said tip height to provide an exposed tip portion on a distal end of said protruding integral TSV tip, and 
 a workpiece comprising a plurality of contact sites, wherein said IC die is mounted face-up to said workpiece, said exposed tip portion of said TSVs bonded to respective ones of said plurality of contact sites of said workpiece. 
   
     
     
         7 . The electronic assembly of  claim 6 , wherein said workpiece comprises a wafer, another IC die or a package substrate. 
     
     
         8 . The electronic assembly of  claim 6 , wherein said electronic assembly includes solder joints for bonding TSVs to respective ones of said plurality of contact sites of said workpiece. 
     
     
         9 . The electronic assembly of  claim 6 , wherein said tip height is 10 to 40 μm. 
     
     
         10 . The electronic assembly of  claim 6 , wherein said electrically conductive filler material comprises copper or tungsten and said dielectric liner comprises silicon oxide, silicon nitride, silicon oxynitride or a polyimide. 
     
     
         11 . The electronic assembly of  claim 6 , wherein said electrically conductive filler material comprises at least one metal, wherein a concentration of said metal on said bottom surface of said substrate is <1×10 12  atoms/cm 2 . 
     
     
         12 . The electronic assembly of  claim 6 , wherein substrate comprises a bulk silicon comprising substrate, said electrically conductive filler material comprises copper or tungsten, and said dielectric liner comprises silicon oxide, silicon nitride, silicon oxynitride or a polyimide.