Semiconductor device and manufacturing method of the same

Abstract

To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film, the width of a region with a small thickness of a gate electrode can be freely set, and the widths of two LDD regions capable of being formed in a self-aligned manner with the gate electrode as a mask can be different in accordance with each circuit. In one TFT, both of two LDD regions with different widths overlap a gate electrode.

1 . A semiconductor device comprising:
 a semiconductor layer over a substrate having an insulating surface;   a gate insulating layer over the semiconductor layer; and   a gate electrode over the gate insulating layer, the gate electrode comprising a first conductive layer and a second conductive layer, wherein the second conductive layer is formed on the first conductive layer,   wherein the semiconductor layer comprises a source region, a drain region, a channel forming region, a first impurity region, and a second impurity region,   wherein the first impurity region is provided between the channel forming region and one of the source region and the drain region,   wherein the second impurity region is provided between the channel forming region and the other of the source region and the drain region,   wherein the first conductive layer overlaps the channel forming region, the first impurity region and the second impurity region,   wherein the second conductive layer overlaps the channel forming region,   wherein a width of the second impurity region is larger than that of the first impurity region, and   wherein a width of the first conductive layer is larger than that of the second conductive layer.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first impurity region and the second impurity region contain an n-type or a p-type impurity element at a lower concentration than that in the source region and the drain region. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the first conductive layer and the second conductive layer are formed of different materials to each other. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein a thickness of the first conductive layer is smaller than that of the second conductive layer. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the width of the first conductive layer is equal to sum of widths of the first impurity region, the channel forming region and the second impurity region. 
     
     
         6 . A semiconductor device comprising a first thin film transistor including a first semiconductor layer and a second thin film transistor including a second semiconductor layer over a substrate, comprising:
 the first semiconductor layer and the second semiconductor layer over the substrate having an insulating surface;   a gate insulating layer over the first semiconductor layer and the second semiconductor layer;   a first gate electrode over the first semiconductor layer with the gate insulating layer interposed therebetween, the first gate electrode comprising a first conductive layer and a second conductive layer, wherein the second conductive layer is formed on the first conductive layer; and   a second gate electrode over the second semiconductor layer with the gate insulating layer interposed therebetween, the second gate electrode comprising a third conductive layer and a fourth conductive layer, wherein the fourth conductive layer is formed on the third conductive layer,   wherein the first semiconductor layer comprises a first channel forming region, a first source region, a first drain region, a first impurity region, and a second impurity region,   wherein the first impurity region is provided between the first channel forming region and one of the first source region and the first drain region,   wherein the second impurity region is provided between the first channel forming region and the other of the first source region and the first drain region,   wherein a width of the first impurity region is larger than that of the second impurity region,   wherein the first channel forming region overlaps the first gate electrode through the gate insulating layer,   wherein the first conductive layer overlaps the first channel forming region, the first impurity region, and the second impurity region,   wherein the second conductive layer overlaps the first channel forming region,   wherein the second semiconductor layer comprises a second channel forming region, a second source region, a second drain region, and a third impurity region and a fourth impurity region,   wherein the third impurity region is provided between the second channel forming region and one of the second source region and the second drain region,   wherein the fourth impurity region is provided between the second channel forming region and the other of the second source region and the second drain region,   wherein the second channel forming region overlaps the second gate electrode through the gate insulating layer,   wherein the third conductive layer overlaps the second channel forming region, the third impurity region and the fourth impurity region, and   wherein the fourth conductive layer overlaps the second channel forming region.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the first impurity region and the second impurity region comprise an n-type or a p-type impurity element at a lower concentration than that in the first source region and the first drain region. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein the first impurity region and the second impurity region comprise an n-type or a p-type impurity element at the same concentration as that in the third impurity region and the fourth impurity region. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein the first thin film transistor is included in a driver circuit. 
     
     
         10 . The semiconductor device according to  claim 6 , wherein the second thin film transistor is included in a pixel circuit. 
     
     
         11 . The semiconductor device according to  claim 6 , wherein a width of the first conductive layer is larger than that of the second conductive layer. 
     
     
         12 . The semiconductor device according to  claim 6 , wherein a width of the third conductive layer is larger than that of the fourth conductive layer. 
     
     
         13 . A semiconductor device comprising:
 a semiconductor layer over a substrate having an insulating surface;   a gate insulating layer over the semiconductor layer; and   a gate electrode over the gate insulating layer, the gate electrode comprising a first conductive layer and a second conductive layer, wherein the second conductive layer is formed on the first conductive layer,   wherein the semiconductor layer comprises a source region, a drain region, a channel forming region, a first impurity region, and a second impurity region,   wherein the first impurity region is provided between the channel forming region and one of the source region and the drain region,   wherein the second impurity region is provided between the channel forming region and the other of the source region and the drain region.   wherein the first conductive layer comprises a first region, a second region, and a third region,   wherein the second region is provided between the first region and the third region,   wherein the second conductive layer is provided over the second region, and   wherein a width of the first region is larger than that of the third region.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein the first impurity region and the second impurity region contain an n-type or a p-type impurity element at a lower concentration than that in the source region and the drain region. 
     
     
         15 . The semiconductor device according to  claim 13 , wherein the first conductive layer and the second conductive layer are formed of different materials to each other. 
     
     
         16 . The semiconductor device according to  claim 13 , wherein a thickness of the first conductive layer is smaller than that of the second conductive layer. 
     
     
         17 . The semiconductor device according to  claim 13 , wherein a width of the first conductive layer is equal to sum of widths of the first impurity region, the channel forming region and the second impurity region. 
     
     
         18 . The semiconductor device according to  claim 13 ,
 wherein the first region is overlapped with the first impurity region, and   wherein the third region is overlapped with the second impurity region.