Memory management for a mobile multimedia processor

Abstract

Certain embodiments of the invention may be found in a method for memory management for a mobile multimedia processor. The method may comprise receiving within a mobile multimedia processor chip a plurality of memory requests, and setting a priority level for each of the plurality of received memory requests. Memory from one or both of at least one on-chip memory block and at least one off-chip memory block may be allocated, and one or more of the plurality of received memory requests may be handled, using the allocated memory, based on a corresponding set priority level and at least one dynamically settable memory allocation priority threshold. The priority level may be set based on an expected number of memory accesses and/or a total number of memory accesses per unit time. The off-chip memory block may be placed into a power-saving mode.

1 - 91 . (canceled) 
     
     
         92 . A method, comprising:
 in a multimedia processor chip:
 receiving a plurality of memory requests; 
 setting a priority level for each of said plurality of received memory requests; 
 allocating memory from one or both of at least one on-chip memory block and/or at least one off-chip memory block; and 
 handling one or more of said plurality of received memory requests based on a corresponding said set priority level and at least one dynamically settable memory allocation priority threshold. 
   
     
     
         93 . The method according to  claim 92 , comprising setting said priority level based on an expected number of memory accesses. 
     
     
         94 . The method according to  claim 92 , comprising setting said priority level based on a total number of memory accesses per unit time. 
     
     
         95 . The method according to  claim 92 , comprising placing said off-chip memory block in a power-saving mode. 
     
     
         96 . A machine-readable storage having stored thereon, a computer program having at least one code section for managing memory, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
 receiving within a mobile multimedia processor chip a plurality of memory requests;   setting a priority level for each of said plurality of received memory requests;   allocating memory from one or both of: at least one on-chip memory block and/or at least one off-chip memory block;; and   handling one or more of said plurality of received memory requests based on a corresponding said set priority level and at least one dynamically settable memory allocation priority threshold.   
     
     
         97 . The machine-readable storage according to  claim 96 , wherein the at least one code section comprises code for setting said priority level based on an expected number of memory accesses. 
     
     
         98 . The machine-readable storage according to  claim 96 , wherein the at least one code section comprises code for setting said priority level based on a total number of memory accesses per unit time. 
     
     
         99 . The machine-readable storage according to  claim 96 , wherein the at least one code section comprises code for placing said off-chip memory block in a power-saving mode. 
     
     
         100 . A system for managing memory, the system comprising:
 one or more circuits for use within a mobile multimedia processor chip, said one or more circuits being operable to:
 receive a plurality of memory requests; 
 set a priority level for each of said plurality of received memory requests; 
 allocate memory from one or both of: at least one on-chip memory block and/or at least one off-chip memory block; and 
 handle one or more of said plurality of received memory requests based on a corresponding said set priority level and at least one dynamically settable memory allocation priority threshold. 
   
     
     
         101 . The system according to  claim 100 , wherein said one or more circuits are operable for setting said priority level based on an expected number of memory accesses. 
     
     
         102 . The system according to  claim 100 , wherein said one or more circuits are operable for setting said priority level based on a total number of memory accesses per unit time. 
     
     
         103 . The system according to  claim 100 , wherein said one or more circuits are operable for placing said off-chip memory block in a power-saving mode. 
     
     
         104 . A method for managing memory, the method comprising:
 in a mobile multimedia processor chip:
 receiving a plurality of memory requests; 
 allocating memory from one or both of: at least one on-chip memory block and/or at least one off-chip memory block based on a priority level; 
 handling one or more of said plurality of received memory requests based on said allocated memory; and 
 placing one or both of said on-chip memory block and/or said off-chip memory block into a power saving mode. 
   
     
     
         105 . The method according to  claim 104 , comprising placing at least a portion of said mobile multimedia processor chip into said power saving mode. 
     
     
         106 . A machine-readable storage having stored thereon, a computer program having at least one code section for managing memory, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
 receiving within a mobile multimedia processor chip a plurality of memory requests;   allocating memory from one or both of: at least one on-chip memory block and/or at least one off-chip memory block based on a priority level;   handling one or more of said plurality of received memory requests based on said allocated memory; and   placing one or both of said on-chip memory block and/or said off-chip memory block into a power saving mode.   
     
     
         107 . The machine-readable storage according to  claim 106 , wherein the at least one code section comprises code for placing at least a portion of said mobile multimedia processor chip into said power saving mode. 
     
     
         108 . A system for managing memory, the system comprising:
 one or more circuits for use within a mobile multimedia processor chip, said one or more circuits being operable to:
 receive a plurality of memory requests; 
 allocate memory from one or both of: at least one on-chip memory block and/or at least one off-chip memory block based on a priority level; 
 handle one or more of said plurality of received memory requests based on said allocated memory; and 
 place one or both of said on-chip memory block and/or said off-chip memory block into a power saving mode. 
   
     
     
         109 . The system according to  claim 108 , wherein said one or more circuits are operable for placing at least a portion of said mobile multimedia processor chip into said power saving mode. 
     
     
         110 . A mobile device, comprising:
 a multimedia processor;   an embedded memory;   an external memory operably coupled to said multimedia processor; and   one or more circuits operable to implement a priority-based memory allocation scheme, wherein a portion of memory is allocated from one or both of the embedded memory and/or the external memory, based on at least one set priority level for each memory request and at least one dynamically settable memory allocation priority threshold.   
     
     
         111 . The mobile device of  claim 110 , wherein said portion of memory that is allocated is entirely from said embedded memory. 
     
     
         112 . The mobile device of  claim 110 , wherein said portion of memory that is allocated memory is entirely from said external memory. 
     
     
         113 . The mobile device of  claim 110 , wherein said external memory comprises non-volatile memory. 
     
     
         114 . The mobile device of  claim 110 , wherein said external memory comprises FLASH memory. 
     
     
         115 . The mobile device of  claim 110 , wherein said external memory is operably coupled to said multimedia processor via a memorystick pro interface. 
     
     
         116 . The mobile device of  claim 110 , wherein said external memory is operably coupled to said multimedia processor via a SD card interface. 
     
     
         117 . The mobile device of  claim 110 , wherein said external memory is operably coupled to said multimedia processor via a multimedia card interface. 
     
     
         118 . The mobile device of  claim 110 , wherein said external memory is operably coupled to said multimedia processor via a xD card interface. 
     
     
         119 . The mobile device of  claim 110 , wherein said external memory is capable of being removed from the mobile device by a user. 
     
     
         120 . The mobile device of  claim 110 , wherein said external memory is operably coupled to said multimedia processor via a device external to a device that houses said multimedia processor.