Circuit Arrangement for Overtemperature Detection

Abstract

A method and system is provided for retrieving information about operational data from a plurality of building systems and service and maintenance information for a plurality of building sites. A customer web portal is provided with a database for storing the operational data and the service information allowing users to more readily generate reports and obtain service related information for a plurality of sites without having to maintain separate database systems at remote locations.

1 . A circuit arrangement for detecting the overtemperature of a semiconductor body, the circuit arrangement comprising:
 at least one field effect transistor including a load terminal;   a parasitic diode integrated in the semiconductor body, the parasitic diode connecting the load terminal of the field effect transistor to a bulk terminal of the semiconductor body;   an evaluating unit electrically connected to the parasitic diode via the bulk terminal at the semiconductor body, the evaluating unit configured to feed a current into the parasitic diode and evaluate a temperature-dependent voltage drop across the parasitic diode, the direction of the current fed into the diode being such that it is operated in the forward direction;   wherein the evaluating unit comprises a short circuit device operable to temporarily short circuit the parasitic diode.   
     
     
         2 . The circuit arrangement as claimed in  claim 1  wherein the field effect transistor is provided as a power transistor structure. 
     
     
         3 . The circuit arrangement as claimed in  claim 1 , wherein the field effect transistor provides a power transistor structure, wherein the short circuit device is configured to short circuit the parasitic diode when the field effect transistor is switched on and a voltage occurs along a drain-source path of the power transistor structure which is above a preset comparison voltage. 
     
     
         4 . The circuit arrangement as claimed in  claim 1 , wherein the short circuit device is configured to short circuit the parasitic diode when the field effect transistor is switched off and a voltage occurs at a drain terminal of the power transistor structure which is above a preset comparison voltage. 
     
     
         5 . The circuit arrangement as claimed in  claim 1 , wherein the short circuit device is configured to short circuit the parasitic diode if an operating voltage, which is above a preset comparison voltage, provides for an excessive voltage at a drain terminal of the power transistor structure. 
     
     
         6 . The circuit arrangement as claimed in  claim 1 , wherein the short circuit device includes a switching element, and wherein the evaluating unit is an external evaluating unit, the short circuit device being arranged in the external evaluating unit. 
     
     
         7 . The circuit arrangement as claimed in  claim 1 , wherein the field effect transistor includes a load path, wherein the parasitic diode is connected to a further parasitic diode as diodes in series opposition, and wherein the diodes in series opposition are connected in parallel with the load path of the field effect transistor. 
     
     
         8 . The circuit arrangement as claimed in  claim 1 , wherein the evaluating unit is thermally decoupled and arranged separately from the semiconductor body. 
     
     
         9 . The circuit arrangement as claimed in  claim 1 , wherein the evaluating unit is configured to compare the voltage drop across the parasitic diode with a preset comparison voltage. 
     
     
         10 . The circuit arrangement as claimed in  claim 1 , wherein the evaluating unit is configured to compare the voltage drop across a diode structure in the evaluating unit with a comparison voltage dependent on the temperature of the evaluating unit. 
     
     
         11 . The circuit arrangement as claimed in  claim 9 , wherein the evaluating unit is configured to generate an overtemperature detection signal when a predeterminable difference of the voltage drop across the parasitic diode and the preset comparison voltage is reached. 
     
     
         12 . The circuit arrangement of  claim 10 , wherein the evaluating unit comprises current/voltage converters configured to convert the voltage drop across the diode structure and/or the comparison voltage into currents. 
     
     
         13 . The circuit arrangement as claimed in  claim 12 , wherein the evaluating unit is configured to generate an overtemperature detection signal when a predetermined difference of the currents is reached. 
     
     
         14 . The circuit arrangement as claimed in  claim 10 , wherein the current/voltage converters comprise resistor components of the same material. 
     
     
         15 . The circuit arrangement as claimed in  claim 1 , wherein the voltage across a load path of the field effect transistor is monitored. 
     
     
         16 . The circuit arrangement as claimed in  claim 1 , wherein the evaluating unit is configured to be activated or deactivated by an external signal. 
     
     
         17 . The circuit arrangement as claimed in  claim 1 , wherein the parasitic diode is a source-bulk diode inherent in the field effect transistor. 
     
     
         18 . The circuit arrangement as claimed in  claim 7 , wherein the further parasitic diode is a drain-bulk diode inherent in the field effect transistor.