Parallel operation device allowing efficient parallel operational processing

Abstract

In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

1 - 12 . (canceled) 
     
     
         13 . A parallel processing device, comprising plural operational blocks each comprising:
 a data storage unit including a plurality of data entries each including a plurality of memory cells arranged as a memory cell array and arranged corresponding to a respective entry;   a plurality of arithmetic/logic processing elements, each of which couples with a corresponding entry and performs a designated operational processing on data stored in the corresponding entry; and   a plurality of data communication circuits, provided corresponding to the entries, each performing data communication between a corresponding entry and another entry, the plurality of data communication circuits each having entry-to-entry distance and direction of data movement set individually in accordance with operation kind to be performed.   
     
     
         14 . The parallel processing device according to  claim 13 , wherein each of the data communication circuits includes
 a movement data register for storing data for setting an amount of data movement, and   a multiplexer for setting a data transfer path in accordance with the data stored in the movement data register.   
     
     
         15 . The parallel processing device according to  claim 13 , wherein
 each of the arithmetic/logic processing elements includes a plurality of registers for storing data to be processed and mask data for masking the operational processing; and   the movement data register is formed by a register, among the plurality of registers, other than the registers used in the data movement operation.   
     
     
         16 . The parallel processing device according to  claim 13 , wherein
 movement data for setting an amount of the data movement designates one data movement amount among a plurality of predetermined amounts of data movement including direction of data transfer, the entries are arranged successively from an uppermost to a lowermost order, and when destination of movement exceeds the uppermost or lowermost entry in data movement the destination of data movement is designated in a cyclic manner.   
     
     
         17 . A parallel processing device, comprising plural operational blocks each comprising:
 a data storage unit having a plurality of data entries, each data entry including a plurality of memory cells arranged as a memory cell array and arranged corresponding to a respective entry;   a plurality of arithmetic/logic processing elements each of which couples with a corresponding entry and performs a designated operational processing on data stored in the corresponding entry; and   a plurality of data communication circuits, provided corresponding to the entries, each performing data communication between a corresponding entry and another entry, the plurality of data communication circuits each having entry-to-entry distance and direction of data movement set individually in accordance with operation kind to be performed;   data for setting contents of operational processing of each respective arithmetic/logic processing element and data for designating amount of data movement of the data communication circuit being set in an empty register among a plurality of registers storing data to be processed and mask data for masking an operational processing, provided in the respective arithmetic/logic element.