Semiconductor memory device capable of driving non-selected word lines to first and second potentials

Abstract

A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

1 . A semiconductor device including a word line drive circuit having the function of resetting a word line by driving said word line connected to a specific memory cell when said specific memory cell in a memory cell array including a plurality of memory cells is returned from an activated state to a standby state;
 wherein a reset level of said word line drive circuit which is set when the reset operation of said word line is executed can be switched between a first potential and a second potential.   
     
     
         2 . A semiconductor device according to  claim 1 , wherein a reset level switch circuit unit for switching said first potential and said second potential of said reset level is disposed in said word line drive circuit. 
     
     
         3 . A semiconductor device according to  claim 1 , wherein said reset level switch circuit for switching said first potential and said second potential of said reset level is disposed separately from said word line drive circuit. 
     
     
         4 . A semiconductor device including a plurality of word line drive circuits each having the function of resetting a word line by driving said word line connected to a specific memory cell when said specific memory cell inside a memory cell array including a plurality of memory cells is returned from an activated state to a standby state;
 wherein a reset level switch circuit for switching the reset level of a plurality of said word line drive circuits which are set when the reset operation of said word line is executed, between a first potential and a second potential, is disposed separately from said word line drive circuits, and the switching operation of said reset level between said first potential and said second potential by said reset level switch circuit is collectively executed for a plurality of said word line drive circuits.   
     
     
         5 . A semiconductor device according to  claim 1 , wherein said second potential is set to a level lower than said first potential. 
     
     
         6 . A semiconductor device according to  claim 1 , wherein said first potential of said reset level is a ground potential and said second potential is a potential of a negative voltage level. 
     
     
         7 . A semiconductor device according to  claim 1 , wherein the switching operation of said reset level to said first potential is executed before the reset operation of said word line is started. 
     
     
         8 . A semiconductor device according to  claim 1 , wherein the switching operation of said reset level to said second potential is executed after said reset operation is started and the level of said word line drops. 
     
     
         9 . A semiconductor device according to  claim 1 , which further includes:
 a reset level switching control timing circuit for setting in advance a period in which the level of said word line drops to a predetermined level after the start of said reset operation, and for switching said reset level from said first potential to said second potential after said period passes from the timing of the start of said reset operation.   
     
     
         10 . A semiconductor device according to  claim 1 , which further includes:
 a word line potential judging circuit for supervising the potential of said word line and switching said reset level from said first potential to said second potential when it detects the drop of the potential of said word line to a predetermined level.   
     
     
         11 . A semiconductor device according to  claim 1 , wherein the switching operation of said reset level between said first potential and said second potential is executed by using an activation signal and a non-activation signal for activating and non-activating a sense amplifier provided to said memory cell array. 
     
     
         12 . A semiconductor device according to  claim 2 , wherein said second potential is set to a level lower than said first potential. 
     
     
         13 . A semiconductor device according to  claim 2 , wherein said first potential of said reset level is a ground potential and said second potential is a potential of a negative voltage level. 
     
     
         14 . A semiconductor device according to  claim 2 , wherein the switching operation of said reset level to said first potential is executed before the reset operation of said word line is started. 
     
     
         15 . A semiconductor device according to  claim 2 , wherein the switching operation of said reset level to said second potential is executed after said reset operation is started and the level of said word line drops. 
     
     
         16 . A semiconductor device according to  claim 2 , which further includes:
 a reset level switching control timing circuit for setting in advance a period in which the level of said word line drops to a predetermined level after the start of said reset operation, and for switching said reset level from said first potential to said second potential after said period passes from the timing of the start of said reset operation.   
     
     
         17 . A semiconductor device according to  claim 2 , which further includes:
 a word line potential judging circuit for supervising the potential of said word line and switching said reset level from said first potential to said second potential when it detects the drop of the potential of said word line to a predetermined level.   
     
     
         18 . A semiconductor device according to  claim 2 , wherein the switching operation of said reset level between said first potential and said second potential is executed by using an activation signal and a non-activation signal for activating and non-activating a sense amplifier provided to said memory cell array. 
     
     
         19 . A semiconductor device according to  claim 3 , wherein said second potential is set to a level lower than said first potential. 
     
     
         20 . A semiconductor device according to  claim 3 , wherein said first potential of said reset level is a ground potential and said second potential is a potential of a negative voltage level. 
     
     
         21 . A semiconductor device according to  claim 3 , wherein the switching operation of said reset level to said first potential is executed before the reset operation of said word line is started. 
     
     
         22 . A semiconductor device according to  claim 3 , wherein the switching operation of said reset level to said second potential is executed after said reset operation is started and the level of said word line drops. 
     
     
         23 . A semiconductor device according to  claim 3 , which further includes:
 a reset level switching control timing circuit for setting in advance a period in which the level of said word line drops to a predetermined level after the start of said reset operation, and switching said reset level from said first potential to said second potential after said period passes from the timing of the start of said reset operation.   
     
     
         24 . A semiconductor device according to  claim 3 , which further includes:
 a word line potential judging circuit for supervising the potential of said word line, and switching said reset level from said first potential to said second potential when it detects the drop of the potential of said word line to a predetermined level.   
     
     
         25 . A semiconductor device according to  claim 3 , wherein the switching operation of said reset level between said first potential and said second potential is executed by using an activation signal and a non-activation signal for activating and non-activating a sense amplifier provided to said memory cell array. 
     
     
         26 . A semiconductor device according to  claim 4 , wherein said second potential is set to a level lower than said first potential. 
     
     
         27 . A semiconductor device according to  claim 4 , wherein said first potential of said reset level is a ground potential and said second potential is a potential having a negative voltage level. 
     
     
         28 . A semiconductor device according to  claim 4 , wherein the switching operation of said reset level to said first potential is executed before the start of the reset operation of said word line. 
     
     
         29 . A semiconductor device according to  claim 4 , wherein the switching operation of said reset level to said second potential is executed after said reset operation is started and the level of said word line drops. 
     
     
         30 . A semiconductor device according to  claim 4 , which further includes:
 a reset level switching control timing circuit for setting in advance a period in which the level of said word line drops to a predetermined level from the start of said reset operation, and switching said reset level from said first potential to said second potential after said period passes from the timing of the start of said reset operation.   
     
     
         31 . A semiconductor device according to  claim 4 , which further includes:
 a word line potential judging circuit for supervising the potential of said word line and switching said reset level from said first potential to said second potential when it detects the drop of the potential of said word line to a predetermined level.   
     
     
         32 . A semiconductor device according to  claim 4 , wherein the switching operation of said reset level between said first potential and said second potential is executed by using an activation signal and a non-activation signal for activating and non-activating a sense amplifier provided to said memory cell array. 
     
     
         33 . A semiconductor device according to  claim 5 , wherein the switching operation of said reset level to said first potential is executed before the start of the reset operation of said word line. 
     
     
         34 . A semiconductor device according to  claim 5 , wherein the switching operation of said reset level to said second potential is executed after said reset operation is started and the level of said word line drops. 
     
     
         35 . A semiconductor device according to  claim 5 , which further includes:
 a reset level switching control timing circuit for setting in advance a period in which the level of said word line drops to a predetermined level after the start of said reset operation, and switching said reset level from said first potential to said second potential after said period passes from the timing of the start of said reset operation.   
     
     
         36 . A semiconductor device according to  claim 5 , which further includes:
 a word line potential judging circuit for supervising the potential of said word line, and switching said reset level from said first potential to said second potential when it detects the drop of the potential of said word line to a predetermined level.   
     
     
         37 . A semiconductor device according to  claim 5 , wherein the switching operation of said reset level between said first potential and said second potential is executed by using an activation signal and a non-activation signal for activating and non-activating a sense amplifier provided to said memory cell array. 
     
     
         38 . A semiconductor device according to  claim 6 , wherein the switching operation of said reset level to said first potential is executed before the start of the reset operation of said word line. 
     
     
         39 . A semiconductor device according to  claim 6 , wherein the switching operation of said reset level to said second potential is executed after said reset operation is started and the level of said word line drops. 
     
     
         40 . A semiconductor device according to  claim 6 , which further includes:
 a reset level switching control timing circuit for setting in advance a period in which the level of said word line drops to a predetermined level after the start of said reset operation, and switching said reset level from said first potential to said second potential after said period passes from the timing of the start of said reset operation.   
     
     
         41 . A semiconductor device according to  claim 6 , which further includes:
 a word line potential judging circuit for supervising the potential of said word line, and switching said reset level from said first potential to said second potential when it detects the drop of the potential of said word line to a predetermined level.   
     
     
         42 . A semiconductor device according to  claim 6 , wherein the switching operation of said reset level between said first potential and said second potential is carried out by using an activation signal and a non-activation signal for activating and non-activating a sense amplifier provided to said memory cell array. 
     
     
         43 . A semiconductor device including:
 a plurality of word lines disposed in parallel;   a plurality of bit lines extending in a direction perpendicular to the extending direction of said word lines;   a memory cell array having a plurality of memory cells disposed in an array form in such a manner as to correspond to said word lines and to said bit lines, and connected to corresponding ones of said word lines and said bit lines; and   a word line reset level generating circuit for generating a negative potential;   wherein non-selected ones of said word lines are set to a negative potential by applying the output of said word line reset level generating circuit to non-selected ones of said word lines; and   wherein said word line reset level generating circuit changes the amount of a current supply of said negative potential in accordance with the operation of said memory cell array.   
     
     
         44 . A semiconductor device according to  claim 43 , which further includes:
 a word line reset level detecting circuit for detecting the output state of said word line reset level generating circuit; and   a word line reset level control circuit for controlling the operation of said word line reset level generating circuit on the basis of the detection result of said reset level detecting circuit.   
     
     
         45 . A semiconductor device according to  claim 44 , wherein, when the output of said word line reset level generating circuit is lower than a first predetermined voltage, said reset level control circuit stops the operation of said word line reset level generating circuit; when the output of said word line reset level generating circuit is higher than a second predetermined voltage, said reset level control circuit operates said word line reset level generating circuit so that the amount of the current supply thereof becomes maximum; and when the output of said word line reset level generating circuit is between said first and second predetermined voltages, said reset level control circuit controls the amount of the current supply of said word line reset level generating circuit in accordance with the operation of said memory cell array. 
     
     
         46 . A semiconductor device according to  claim 43 , said semiconductor device comprising a plurality of banks;
 wherein said word line reset level generating circuit comprises a plurality of circuit units corresponding to a plurality of said banks, and capable of operating independently; and   wherein a plurality of said circuit units are selected and operated in accordance with the operation of said memory cell array.   
     
     
         47 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is higher than a higher potential of a power source of said oscillation circuit. 
     
     
         48 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is equal to a higher potential of a power source of said oscillation circuit. 
     
     
         49 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is lower than a higher potential of a power source of said oscillation circuit. 
     
     
         50 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor, a capacitor drive circuit for driving said capacitor, and a power source switch circuit for switching the connection of a power source line of higher potential of said capacitor drive circuit among a plurality of power source lines having different potentials. 
     
     
         51 . A semiconductor device according to  claim 44 , said semiconductor device comprising a plurality of banks;
 wherein said word line reset level generating circuit comprises a plurality of circuit units corresponding to a plurality of said banks, and capable of operating independently; and   wherein a plurality of said circuit units are selected and operated in accordance with the operation of said memory cell array.   
     
     
         52 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is higher than a higher potential of a power source of said oscillation circuit. 
     
     
         53 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is equal to a higher potential of a power source of said oscillation circuit. 
     
     
         54 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is lower than a higher potential of a power source of said oscillation circuit. 
     
     
         55 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor, a capacitor drive circuit for driving said capacitor and a power source switch circuit for switching the connection of a power source line of higher potential of said capacitor drive circuit among a plurality of power source lines having different potentials. 
     
     
         56 . A semiconductor device according to  claim 45 , said semiconductor device comprising a plurality of banks;
 wherein said word line reset level generating circuit comprises a plurality of circuit units corresponding to a plurality of said banks and capable of operating independently; and   wherein a plurality of said circuit units are selected and operated in accordance with the operation of said memory cell array.   
     
     
         57 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is higher than a higher potential of a power source of said oscillation circuit. 
     
     
         58 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is equal to a higher potential of a power source of said oscillation circuit. 
     
     
         59 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and a higher potential of a power source of said capacitor drive circuit is lower than a higher potential of a power source of said oscillation circuit. 
     
     
         60 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor, a capacitor drive circuit for driving said capacitor and a power source switch circuit for switching the connection of a power source line of higher potential of said capacitor drive circuit among a plurality of power source lines having different potentials. 
     
     
         61 . A semiconductor device according to  claim 50 , wherein said power source switch circuit executes the switching operation between a power source line having a potential higher than a higher potential of a power source of said oscillation circuit and a power source line having a potential equal to a higher potential of a power source of said oscillation circuit. 
     
     
         62 . A semiconductor device according to  claim 55 , wherein said power source switch circuit executes the switching operation between a power source line having a potential higher than a higher potential of a power source of said oscillation circuit and a power source line having a potential equal to a higher potential of a power source of said oscillation circuit. 
     
     
         63 . A semiconductor device according to  claim 60 , wherein said power source switch circuit executes the switching operation between a power source line having a potential higher than a higher potential of a power source of said oscillation circuit and a power source line having a potential equal to a higher potential of a power source of said oscillation circuit. 
     
     
         64 . A semiconductor device according to  claim 50 , wherein said power source switch circuit executes the switching operation between a power source line having a potential equal to a higher potential of a power source of said oscillation circuit and a power source line having a potential lower than a higher potential of a power source of said oscillation circuit. 
     
     
         65 . A semiconductor device according to  claim 55 , wherein said power source switch circuit executes the switching operation between a power source line having a potential equal to a higher potential of a power source of said oscillation circuit and a power source line having a potential lower than a higher potential of a power source of said oscillation circuit. 
     
     
         66 . A semiconductor device according to  claim 60 , wherein said power source switch circuit executes the switching operation between a power source line having a potential equal to a higher potential of a power source of said oscillation circuit and a power source line having a potential lower than a higher potential of a power source of said oscillation circuit. 
     
     
         67 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and said capacitor drive circuit applies a single oscillation signal outputted from said oscillation circuit to said capacitor. 
     
     
         68 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and said capacitor drive circuit applies a plurality of oscillation signals outputted from said oscillation circuit to said capacitor. 
     
     
         69 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes a plurality of oscillation circuit for outputting oscillation signals having different frequencies, a capacitor, a capacitor drive circuit for driving said capacitor and a selection circuit for selecting the oscillation signal from a plurality of said oscillation circuits to be supplied to said capacitor drive circuit. 
     
     
         70 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes a plurality of oscillation circuits for outputting oscillation signals having different frequencies, a capacitor, a power source switch circuit for switching the connection of a power source line of higher potential of a capacitor drive circuit for driving said capacitor among a plurality of power source lines having different potentials, and a selection circuit for selecting the oscillation signal from a plurality of said oscillation circuits to be supplied to said capacitor drive circuit. 
     
     
         71 . A semiconductor device according to  claim 43 , wherein said word line reset level generating circuit includes an oscillation circuit, a plurality of capacitor units, a plurality of capacitor drive circuit units each being for driving each of said capacitor units, and a switch for switching the input of the oscillation signal outputted from said oscillation circuit to each of said capacitor drive circuit units, and said switch is switched in accordance with the operation of said memory cell array. 
     
     
         72 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and said capacitor drive circuit applies a single oscillation signal outputted from said oscillation circuit to said capacitor. 
     
     
         73 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and said capacitor drive circuit applies a plurality of oscillation signals outputted from said oscillation circuit to said capacitor. 
     
     
         74 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes a plurality of oscillation circuits for outputting oscillation signals having different frequencies, a capacitor, a capacitor drive circuit and a selection circuit for selecting the oscillation signal from a plurality of oscillation circuits to be supplied to said capacitor drive circuit. 
     
     
         75 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes a plurality of oscillation circuits for outputting oscillation signals having different frequencies, a capacitor, a power source switch circuit for switching the connection of a power source line of higher potential of a capacitor drive circuit for driving said capacitor among a plurality of power source lines having different potentials, and a selection circuit for selecting the oscillation signal to be supplied to said capacitor drive circuit from the outputs of a plurality of said oscillation circuits. 
     
     
         76 . A semiconductor device according to  claim 44 , wherein said word line reset level generating circuit includes an oscillation circuit, a plurality of capacitor units, a plurality of capacitor drive circuit units each being for driving each of said capacitor units, and a switch for switching the input of the oscillation signal outputted from said oscillation circuit to each of said capacitor drive circuit units, and said switch is switched in accordance with the operation of said memory cell array. 
     
     
         77 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and said capacitor drive circuit applies a single oscillation signal outputted from said oscillation circuit to said capacitor. 
     
     
         78 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes an oscillation circuit, a capacitor and a capacitor drive circuit for driving said capacitor, and said capacitor drive circuit applies a plurality of oscillation signals outputted from said oscillation circuit to said capacitor. 
     
     
         79 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes a plurality of oscillation circuits for outputting oscillation signals having different frequencies, a capacitor, a capacitor drive circuit for driving said capacitor and a selection circuit for selecting the oscillation signal from a plurality of said oscillation circuits to be supplied to said capacitor drive circuit. 
     
     
         80 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes a plurality of oscillation circuits for outputting oscillation signals having different frequencies, a capacitor, a power source switch circuit for switching the connection of a power source line of higher potential of a capacitor drive circuit for driving said capacitor among a plurality of power source lines having different potentials, and a selection circuit for selecting the oscillation signal from a plurality of said oscillation circuits to be supplied to said capacitor drive circuit. 
     
     
         81 . A semiconductor device according to  claim 45 , wherein said word line reset level generating circuit includes an oscillation circuit, a plurality of capacitor units, a plurality of capacitor drive circuit units each being for driving each of said capacitor units and a switch for switching the input of the oscillation signal outputted from said oscillation circuit to each of said capacitor drive circuit units, and said switch is switched in accordance with the operation of said memory cell array. 
     
     
         82 . A semiconductor device according to  claim 47 , which further includes:
 an internal regulator circuit for down-converting a power source voltage supplied from outside, and a higher potential of a power source of said oscillation circuit is supplied from said internal regulator circuit.   
     
     
         83 . A semiconductor device according to  claim 52 , which further includes:
 an internal regulator circuit for down-converting a power source voltage supplied from outside, and a higher potential of a power source of said oscillation circuit is supplied from said internal regulator circuit.   
     
     
         84 . A semiconductor device according to  claim 57 , which further includes:
 an internal regulator circuit for down-converting a power source voltage supplied from outside, and a higher potential of a power source of said oscillation circuit is supplied from said internal regulator circuit.   
     
     
         85 . A semiconductor device comprising a plurality of power source circuits each having an oscillation circuit and a capacitor, for generating a different potential by driving said capacitor by the oscillation signal outputted from said oscillation circuit:
 wherein at least a part of a plurality of said power source circuits shares in common said oscillation circuit, and drives different one of said capacitors by the oscillation signal outputted from said common oscillation circuit.   
     
     
         86 . A semiconductor device according to  claim 85 , wherein said power source circuit is equipped with an operation control circuit at an input portion to said capacitor drive circuit of the oscillation signal outputted from said common oscillation circuit. 
     
     
         87 . A semiconductor device according to  claim 85 , wherein said power source circuits sharing in common said oscillation circuit generate different potentials. 
     
     
         88 . A semiconductor device according to  claim 85 , wherein said common oscillation circuit outputs a plurality of oscillation signals having different phases, and said capacitor is driven by one of a plurality of said oscillation signals having different phases. 
     
     
         89 . A semiconductor device according to  claim 88 , wherein said power source circuits having said capacitor driven by a plurality of said oscillation signals having different phases generate the same potential, and the outputs of said power source circuits are connected in common. 
     
     
         90 . A semiconductor device according to  claim 89 , wherein said power circuit includes:
 an operation control circuit provided at an input portion of said oscillation signal outputted from said common oscillation circuit to said capacitor drive circuit, and switching the operating state of said power source circuit between an operating state and a non-operating state; and   a potential detecting circuit for detecting the potential generated by said power source circuit;   wherein said operation control circuit is controlled on the basis of the detection result of said potential detecting circuit.   
     
     
         91 . A semiconductor device comprising a plurality of power source circuits, each including a clock input circuit for receiving a clock inputted from outside and a capacitor, and generating different potentials by driving said capacitor by an internal clock for power source outputted from said clock input circuit. 
     
     
         92 . A semiconductor device according to  claim 91 , wherein said clock input circuit includes a frequency dividing circuit for frequency-dividing said clock, and the output of said frequency dividing circuit is outputted as the internal clock for power source. 
     
     
         93 . A semiconductor device according to  claim 85 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         94 . A semiconductor device according to  claim 86 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         95 . A semiconductor device according to  claim 87 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         96 . A semiconductor device according to  claim 88 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         97 . A semiconductor device according to  claim 91 , wherein said semiconductor device is a dynamic random access memory. 
     
     
         98 . A semiconductor device according to  claim 92 , wherein said semiconductor device is a dynamic random access memory.