Circuit layout structure and method to scale down ic layout

Abstract

A circuit layout structure includes a substrate including a first region and a second region, and a set of conductive lines including a first conductive line and a second conductive line which respectively pass through the first region and the second region, wherein a variable spacing lies between the first conductive line and the second conductive line and the first conductive line and the second conductive line selectively have a first region line width and a second region line width so that the first region line width and the second region line width are substantially different.

1 . A circuit layout structure, including:
 a substrate including a first region and a second region; and   a set of conductive lines comprising a first conductive line and a second conductive line which respectively pass through said first region and said second region, wherein a variable spacing lies between said first conductive line and said second conductive line, and said first conductive line and said second conductive line selectively have a first region line width in said first region and a second region line width in said second region so that said first region line width and said second region line width are substantially different.   
     
     
         2 . The circuit layout structure of  claim 1 , wherein said first region is a shallow trench isolation region and said second region is an active area. 
     
     
         3 . The circuit layout structure of  claim 1 , wherein said set of conductive lines has a 45 degree turn in said first region. 
     
     
         4 . The circuit layout structure of  claim 1 , wherein said set of conductive lines has a 90 degree turn in said first region. 
     
     
         5 . The circuit layout structure of  claim 1 , wherein said first region line width is smaller than said second region line width. 
     
     
         6 . The circuit layout structure of  claim 1 , wherein said set of conductive lines has said second region line width in said first region adjacent to said second region. 
     
     
         7 . The circuit layout structure of  claim 1 , wherein at least one side of said first conductive line aligns with at least one side of said second conductive line. 
     
     
         8 . The circuit layout structure of  claim 1 , wherein said first conductive line and said second conductive line selectively have a first spacing in said first region and a second spacing in said second region so that said first spacing is smaller than said second spacing. 
     
     
         9 . The circuit layout structure of  claim 1 , wherein said first conductive line and said second conductive line selectively have a first pitch in said first region and a second pitch in said second region so that said first pitch is smaller than said second pitch. 
     
     
         10 . The circuit layout structure of  claim 1 , wherein said first conductive line and said second conductive line are respectively in accordance with a first region rule and with a second region rule and said first region rule is different from said second region rule. 
     
     
         11 . A method to scale down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices, comprising:
 providing a circuit layout comprising a set of conductive lines comprising a first conductive line and a second conductive line which respectively pass through a first region and a second region, wherein said first conductive line and said second conductive line selectively have a first region original line width, a first region original spacing and a first region original pitch in said first region and selectively have a second region original line width, a second region original spacing and a second region original pitch in said second region; and   performing a sizing-down operation so that said first conductive line and said second conductive line are respectively in accordance with a first region rule and with a second region rule to selectively have a first region scaled-down line width, a first region scaled-down spacing and a first region scaled-down pitch in said first region, and selectively have a second region original line width, a second region scaled-down spacing and a second region scaled-down pitch in said second region, wherein said first region scaled-down line width and said second region original line width are substantially different.   
     
     
         12 . The method of  claim 11 , wherein said sizing-down operation further comprises:
 performing a preliminary sizing-down operation on said first conductive line and on said second conductive line so that all said line width, said spacing and said pitch are scaled down at the same ratio to obtain said first region scaled-down line width, said first region scaled-down spacing and said first region scaled-down pitch in said first region, and said second region scaled-down pitch in said second region; and   performing a sizing-up operation on said first conductive line and on said second conductive line to obtain said second region original line width and said second region scaled-down spacing in said second region.   
     
     
         13 . The method of  claim 11 , wherein said sizing-down operation further comprises:
 performing a preliminary sizing-down operation on said first conductive line and on said second conductive line so that all said line width, said spacing and said pitch are scaled down at the same ratio; and   performing a preliminary sizing-up operation so that said set of conductive lines has said first region original line width and said second region original line width; and   performing a finish sizing-down operation to obtain said first region scaled-down line width and said first region scaled-down pitch in said first region.   
     
     
         14 . The method of  claim 11 , wherein said first region is a shallow trench isolation region and said second region is an active area. 
     
     
         15 . The method of  claim 11 , wherein said first region rule is smaller than said second region rule. 
     
     
         16 . The method of  claim 11 , wherein said set of conductive lines has a 45 degree turn in said first region. 
     
     
         17 . The method of  claim 11 , wherein said set of conductive lines has a 90 degree turn in said first region. 
     
     
         18 . The method of  claim 11 , wherein said first region line width is smaller than said second region line width. 
     
     
         19 . The method of  claim 11 , wherein said set of conductive lines has said second region original line width of a pre-determined length in said first region adjacent to said second region. 
     
     
         20 . The method of  claim 19 , wherein said pre-determined length is between ⅓-1 of a channel width determined by said set of conductive lines passing said second region. 
     
     
         21 . The method of  claim 19 , wherein said pre-determined length is between ½-⅔ of a channel width determined by said set of conductive lines passing said second region.