Delegating network processor operations to star topology serial bus interfaces

Abstract

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

1 - 25 . (canceled) 
     
     
         26 . A system, comprising:
 a multiple-core processor including a plurality of processor cores; and   a fast messaging network for linking at least two of processor cores together such that at least one processor core can send data to another processor core without going through memory, said fast messaging network configured to be operably coupled to a star topology serial bus interface.   
     
     
         27 . The system of  claim 26 , wherein the fast messaging network is configured to operably couple to a star topology serial bus interface having circuitry for translating the read or write messages received from the fast messaging network. 
     
     
         28 . The system of  claim 27 , wherein the circuitry includes at least one direct memory access circuitry and associated PCIe circuitry. 
     
     
         29 . The system of  claim 26 , wherein the star topology serial bus interface handles messages from the fast messaging network. 
     
     
         30 . The system of  claim 29 , wherein the star topology serial bus interface handles the messages from the fast messaging network using internal queues. 
     
     
         31 . The system of  claim 29 , wherein the star topology serial bus interface handles the messages from the fast messaging network using a round-robin distribution scheme. 
     
     
         32 . The system of  claim 29 , wherein the star topology serial bus interface handles the messages from the fast messaging network using a weighted round-robin distribution scheme. 
     
     
         33 . The system of  claim 29 , wherein the star topology serial bus interface handles the messages from the fast messaging network using an eager round-robin distribution scheme. 
     
     
         34 . The system of  claim 26 , wherein the star topology serial bus interface utilizes a credit-based flow control system. 
     
     
         35 . The system of  claim 26  wherein said star topology serial bus interface is a PCIe serial bus interface. 
     
     
         36 . The system of  claim 26 , further comprising:
 a star topology serial bus interface attached to said fast messaging network, said star topology serial bus interface including a direct memory access (DMA) device configured to allow said fast messaging network memory read or write requests to be implemented as star topology serial bus transaction layer packets (TLP) in response to at least one of said read or write requests.   
     
     
         37 . The system of  claim 26  wherein said star topology serial bus interface is a PCIe serial bus interface, and said system further comprises:
 a PCIe serial bus interface attached to said fast messaging network, said PCIe serial bus interface including a direct memory access (DMA) device configured to allow said fast messaging network memory read or write requests to be implemented as PCIe serial bus transaction layer packets (TLP) in response to at least one of said read or write requests.   
     
     
         38 . The system of  claim 37 , wherein the PCIe bus interface handles the messages from said fast messaging network using internal queues. 
     
     
         39 . The system of  claim 37 , wherein the PCIe bus interface handles the messages from said fast messaging network using a round-robin distribution scheme. 
     
     
         40 . The system of  claim 37 , wherein the PCIe bus interface handles the messages from said fast messaging network using a weighted round-robin distribution scheme. 
     
     
         41 . The system of  claim 37 , wherein the PCIe bus interface handles the messages from said fast messaging network using an eager round-robin distribution scheme. 
     
     
         42 . The system of  claim 37 , wherein the PCIe bus interface utilizes a credit-based flow control system. 
     
     
         43 . A semiconductor device, comprising:
 a multiple-core processor including a plurality of processor cores; and   a fast messaging network for linking at least two of processor cores together such that at least one processor core can send data to another processor core without going through memory, said fast messaging network configured to be operably coupled to a star topology serial bus interface.   
     
     
         44 . The device of  claim 43 , wherein the fast messaging network is configured to operably couple to a star topology serial bus interface having circuitry for translating the read or write messages received from the fast messaging network. 
     
     
         45 . The device of  claim 44 , wherein the circuitry includes at least one direct memory access circuitry and associated PCIe circuitry. 
     
     
         46 . The device of  claim 43 , wherein the star topology serial bus interface handles messages from the fast messaging network. 
     
     
         47 . The device of  claim 46 , wherein the star topology serial bus interface handles the messages from the fast messaging network using internal queues. 
     
     
         48 . The device of  claim 46 , wherein the star topology serial bus interface handles the messages from the fast messaging network using a round-robin distribution scheme. 
     
     
         49 . The device of  claim 43 , further comprising:
 a star topology serial bus interface attached to said fast messaging network, said star topology serial bus interface including a direct memory access (DMA) device configured to allow said fast messaging network memory read or write requests to be implemented as star topology serial bus transaction layer packets (TLP) in response to at least one of said read or write requests.   
     
     
         50 . The device of  claim 43  wherein said star topology serial bus interface is a PCIe serial bus interface, and said device further comprises:
 a PCIe serial bus interface attached to said fast messaging network, said PCIe serial bus interface including a direct memory access (DMA) device configured to allow said fast messaging network memory read or write requests to be implemented as PCIe serial bus transaction layer packets (TLP) in response to at least one of said read or write requests.   
     
     
         51 . A communications subsystem, comprising:
 a multiple-core processor including a plurality of processor cores; and   a fast messaging network for linking at least two of processor cores together such that at least one processor core can send data to another processor core without going through memory, said fast messaging network configured to be operably coupled to a star topology serial bus interface.   
     
     
         52 . The subsystem of  claim 51 , wherein the fast messaging network is configured to operably couple to a star topology serial bus interface having circuitry for translating the read or write messages received from the fast messaging network. 
     
     
         53 . The subsystem of  claim 52 , wherein the circuitry includes at least one direct memory access circuitry and associated PCIe circuitry. 
     
     
         54 . The subsystem of  claim 51 , wherein the star topology serial bus interface handles messages from the fast messaging network. 
     
     
         55 . The subsystem of  claim 54 , wherein the star topology serial bus interface handles the messages from the fast messaging network using internal queues. 
     
     
         56 . The subsystem of  claim 54 , wherein the star topology serial bus interface handles the messages from the fast messaging network using a round-robin distribution scheme. 
     
     
         57 . The subsystem of  claim 51 , further comprising:
 a star topology serial bus interface attached to said fast messaging network, said star topology serial bus interface including a direct memory access (DMA) device configured to allow said fast messaging network memory read or write requests to be implemented as star topology serial bus transaction layer packets (TLP) in response to at least one of said read or write requests.   
     
     
         58 . The subsystem of  claim 51  wherein said star topology serial bus interface is a PCIe serial bus interface, and said subsystem further comprises:
 a PCIe serial bus interface attached to said fast messaging network, said PCIe serial bus interface including a direct memory access (DMA) device configured to allow said fast messaging network memory read or write requests to be implemented as PCIe serial bus transaction layer packets (TLP) in response to at least one of said read or write requests.