Semiconductor device

Abstract

A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

1 . A semiconductor device comprising:
 an SOI substrate having a semiconductor substrate, a buried oxide film formed on said semiconductor substrate, and an SOI layer having a first conductivity type formed on said buried oxide film; and   at least one MOS transistor provided on said SOI layer, wherein   said at least one MOS transistor comprises:   a source region and a drain region having a second conductivity type and selectively provided in a surface of said SOI layer;   a body region having a first conductivity type and corresponding to said SOI layer sandwiched between said source region and said drain region;   a gate electrode provided above said body region;   a partial isolation insulation film selectively provided in said SOI layer surface corresponding to a lower part of at least one end of both ends of said gate electrode in a gate width direction, in a peripheral region of an active region comprising said source region, said drain region and said body region;   a semiconductor region provided in said surface of said SOI layer so as to be adjacent to said partial isolation insulation film; and   at least one semiconductor region having a first conductivity type, selectively provided in a surface of said source region in a vicinity of said gate electrode and electrically connected to said body region, wherein,   said partial isolation insulation film has said SOI layer continued from said body region, in a lower part thereof,   said semiconductor region is in contact with said SOI layer under said partial isolation insulation film, and   a region other than the partial isolation insulation film in the peripheral region of said active region is surrounded by a full isolation insulation film penetrating said SOI layer and reaching said buried oxide film.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein,
 said partial isolation insulation film is selectively provided in said SOI layer surface corresponding to lower parts of both ends of said gate electrode in a gate width direction,   said at least one semiconductor region within the electrode region comprises a plurality of semiconductor regions within the electrode region spaced and aligned along said gate electrode, and   said plurality of semiconductor regions are arranged such that a distance between the semiconductor regions, and a distance between an end of said semiconductor regions and a nearest edge of said active region are equal to each other.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein,
 said partial isolation insulation film is selectively provided in said SOI layer surface corresponding to lower parts of both ends of said gate electrode in a gate width direction,   said at least one semiconductor region comprises a plurality of semiconductor regions spaced and aligned along said gate electrode, and   said plurality of semiconductor regions are arranged such that a first distance between an end of said semiconductor regions and a nearest edge of an active region is longer than a second distance between said semiconductor regions.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein said first distance is set so as to be half of said second distance. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein,
 said partial isolation insulation film is selectively provided in said SOI layer surface corresponding to a lower part of one of both ends of said gate electrode in a gate width direction,   said at least one semiconductor region comprises a plurality of semiconductor regions arranged so as to be spaced along said gate electrode, and   said plurality of semiconductor regions are arranged such that a first distance between an end of the semiconductor regions on the side of said partial isolation insulation film is provided and a nearest edge of said active region is longer than a second distance between said semiconductor regions, and a third distance between said end of the semiconductor regions on an opposite side of said partial isolation insulation film and said nearest edge of the active region is shorter than said first distance.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein,
 said at least one MOS transistor comprises a plurality of MOS transistors in which respective gate electrodes are arranged in parallel in a gate length direction, and   said plurality of MOS transistors are provided so as to share said source region between adjacent MOS transistors.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein
 said semiconductor region provided in said source region shared by said adjacent MOS transistors is provided so as to continuously extend between said gate electrodes.   
     
     
         8 . The semiconductor device according to  claim 1 , wherein,
 said at least one MOS transistor comprises an N channel MOS transistor in which said first conductivity type is a P type and said second conductivity type is an N type, and a P channel MOS transistor in which said first conductivity type is an N type and said second conductivity type is a P type,   said at least one semiconductor region in said N channel MOS transistor and said P channel MOS transistor comprises a plurality of semiconductor regions arranged so as to be spaced and aligned along said gate electrode, and   the distance between said semiconductor regions in said N channel MOS transistor is set so as to be smaller than the distance between said semiconductor regions in said P channel MOS transistor.   
     
     
         9 . The semiconductor device according to  claim 1 , further comprising:
 a front semiconductor region having a first conductivity type and selectively provided in said surface of said SOI layer and extending from a side of said semiconductor region on a side of said drain region, to a lower part of said gate electrode, wherein   an impurity concentration of said front semiconductor region is set to be higher than that of said SOI layer and lower than that of said semiconductor region.