Nonvolatile Memory Device and Method of Manufacturing the Same

Abstract

A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.

1 . A method of manufacturing a nonvolatile memory device, the method comprising:
 forming a gate insulating layer and a first conductive layer over first and second areas defined in a semiconductor substrate, wherein selection lines having sidewalls will be formed in the first area and word lines having sidewalls will be formed in the second area;   performing an etch process to lower a height of the first conductive layer in the first area;   forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the conductive layer; and   performing a gate patterning process to form the selection lines and the word lines in the first and second areas, respectively.   
     
     
         2 . The method of  claim 1 , further comprising:
 after performing the gate patterning process,   forming a spacer on the sidewalls of the word lines and the selection lines;   forming an etch-stop layer on a surface of a structure including the spacer, the word lines, and the selection lines; and   forming an interlayer dielectric over the etch-stop layer.   
     
     
         3 . The method of  claim 1 , wherein the etch process is a dry etch process. 
     
     
         4 . The method of  claim 1 , comprising performing the etch process to form a recess mask pattern, having the first area open and the second area closed, over the first conductive layer. 
     
     
         5 . The method of  claim 4 , further comprising forming a buffer layer over the first conductive layer before forming the recess mask pattern. 
     
     
         6 . The method of  claim 1 , wherein an aspect ratio between the selection lines is reduced as much as a reduction in the height of the first conductive layer in the first area. 
     
     
         7 . A nonvolatile memory device, comprising:
 selection lines and word lines formed by sequentially stacking a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate,   wherein a height of the first conductive layer of the selection lines is lower than a height of the first conductive layer of the word lines.   
     
     
         8 . The nonvolatile memory device of  claim 7 , wherein the first conductive layer and the second conductive layer of the selection lines are interconnected through contact holes.