Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

1 - 12 . (canceled) 
     
     
         13 . A semiconductor integrated circuit, comprising:
 a plurality of standard cell rows located side by side in a first direction, each of the standard cell rows including a plurality of standard cells aligned in a second direction which is perpendicular to the first direction, each of the standard cells including one or more gates extended in the first direction,   wherein each of the standard cell rows includes a terminal standard cell at least one end of the standard cell row, the terminal standard cell including two or more supplementary gates, the supplementary gate being a dummy gate or a gate which is a constituent of an inactive transistor.   
     
     
         14 . The semiconductor integrated circuit of  claim 13 , wherein the terminal standard cells in each of the standard cell rows are located at equivalent positions with respect to the second direction. 
     
     
         15 . The semiconductor integrated circuit of  claim 13 , wherein each of the standard cell rows includes the terminal standard cell at each end of the standard cell row. 
     
     
         16 . The semiconductor integrated circuit of  claim 15 , wherein the terminal standard cell includes:
 first and second supplementary gates at both ends with respect to the second direction;   a third supplementary gate adjacent to the first supplementary gate; and   a fourth supplementary gate adjacent to the second supplementary gate.   
     
     
         17 . The semiconductor integrated circuit of  claim 13 , wherein at least one of the terminal standard cells includes a transistor which constitutes a capacitor, a transistor which has a supply potential fixing function, an off-transistor, or a diode. 
     
     
         18 . The semiconductor integrated circuit of  claim 13 , wherein at least one of the terminal standard cells lacks a metal wire for supplying a supply potential to the semiconductor integrated circuit or a diffusion region for supplying a substrate potential to the semiconductor integrated circuit.