Bus system for use with information processing apparatus

Abstract

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

1 . An information processing system comprising:
 a first set of lines for transferring data, address and control signals;   a processor coupled to said first set of lines;   a second set of lines for transferring data, address and control signals;   a memory coupled to said second set of lines;   a third set of lines for transferring data, address and control signals;   a device coupled to said third set of lines; and   a data transfer unit coupled to said first set of lines, said second set of lines and said third set of lines, said data transfer unit for enabling a transfer of data between any arbitrary two of said processor, said memory and said device via corresponding two of said first set of lines, said second set of lines, and said third set of lines.