Shift Registers

Abstract

A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal.

1 . A shift register, comprising
 a plurality of substantially cascaded shift register units, each controlled by a first clock signal and a second clock signal opposite to each other for generating an output signal, wherein the output signal is periodically activated, and each of the shift register units comprises:
 a first switch device for providing the output signal through an output node; 
 a first driving device for driving the first switch device according to a first input signal to activate the output signal; 
 a second driving device, coupled to the second clock signal, for providing the second clock signal according to the first clock signal to drive the first switch device to de-activate the output signal; and 
 a second switch device, coupled to the voltage signal, for providing the voltage signal to the output node according to the second clock signal when the first switch device de-activates the output signal. 
   
     
     
         2 . The shift register as claimed in  claim 1 ,
 wherein each of the shift register units further comprises a third driving device, coupled to the voltage signal, for driving the first switch device to de-activate the output signal by the voltage signal according to a second input signal, and   wherein each of the first and second input signals is periodically activated, and the first input signal, the output signal, and the second input signal are substantially activated.   
     
     
         3 . The shift register as claimed in  claim 2 , wherein the plurality of shift register units comprises first, second, and third substantially cascaded shift register units, the output signal of the first shift register unit serves as the first input signal of the second shift register unit, the output signal of the second shift register unit serves as the first input signal of the third shift register unit and the second input signal of the first shift register, and the output signal of the third shift register unit serves as the second input signal of the second shift register unit. 
     
     
         4 . The shift register as claimed in  claim 1 , wherein each of the shift register units further comprises a third switch device, coupled to the voltage signal, for providing the voltage signal to the output node according to the first clock signal when the first switch device de-activates the output signal. 
     
     
         5 . The shift register as claimed in  claim 1 , wherein each of the shift register units further comprises a fourth switch device, coupled to the voltage signal, for disabling the second driving device by the voltage signal when the first driving device drives the first switch device to activate the output signal. 
     
     
         6 . The shift register as claimed in  claim 1 , wherein the plurality of shift register units comprises first, second, and third substantially cascaded shift register units, the output signal of the first shift register unit serves as the first input signal of the second shift register unit, and the output signal of the second shift register unit. 
     
     
         7 . The shift register as claimed in  claim 1 , wherein the voltage signal is at a low level.